公开(公告)号：US20140063995A1

公开(公告)日：2014-03-06

申请号：US13843681

申请日：2013-03-15

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C8/14 ,  G11C29/702 ,  G11C29/808 ,  G11C29/848

Abstract: A memory may comprise a first bank configured to include first to Nth word lines and first to Mth redundancy word lines to replace M number of word lines among the first to Nth word lines, a second bank configured to include first to Nth word lines and first to Mth redundancy word lines to replace M number of word lines among the first to Nth word lines, and a control circuit configured to activate, in the case where a word line corresponding to an inputted address among the first to Nth word lines in a bank selected between the first bank and the second bank is replaced with a Kth (1≦K≦M) redundancy word line among the first to Mth redundancy word lines during an operation in a first mode, at least one adjacent word line adjacent to the Kth redundancy word line of the selected bank.

Abstract translation: 存储器可以包括配置成包括第一至第N字线和第一至第M冗余字线以替代第一至第N字线中的M个字线的第一存储体，被配置为包括第一至第N字线和第一字线 到第M冗余字线以替换第一至第N字线中的M行字线;以及控制电路，配置为在与银行中的第一至第N字线中输入的地址相对应的字线的情况下， 在第一模式的操作期间，在第一至第M冗余字线之间用第K（1 @ K @ M）个冗余字线替换第一存储体和第二存储体之间的选择，在与第K模式相邻的至少一个相邻字线 所选银行的冗余字线。

公开(公告)号：US20140003178A1

公开(公告)日：2014-01-02

申请号：US13716418

申请日：2012-12-17

Applicant: SK HYNIX INC.

Inventor： Choung-Ki SONG

IPC: G11C11/402

CPC classification number: G11C11/40607 ,  G11C11/402 ,  G11C11/40611 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4067

Abstract: A semiconductor memory device includes a memory cell array configured to include a plurality of word lines, a clock enable buffer configured to receive a clock enable signal, a plurality of command buffers configured to receive a plurality of commands, a refresh control unit configured to sequentially activate the plurality of word lines in a self-refresh mode, a command decoder configured to decode the clock enable signal and the plurality of commands, and to allow the refresh control unit to enter the self-refresh mode or exit from the self-refresh mode, and a buffer control unit configured to disable the plurality of command buffers when the clock enable signal is deactivated, and to enable the plurality of command buffers when the refresh control unit exits from the self-refresh mode.

Abstract translation: 半导体存储器件包括配置为包括多个字线的存储单元阵列，被配置为接收时钟使能信号的时钟使能缓冲器，被配置为接收多个命令的多个命令缓冲器，配置为顺序地配置的刷新控制单元 在自刷新模式下激活多个字线，命令解码器，被配置为对时钟使能信号和多个命令进行解码，并允许刷新控制单元进入自刷新模式或退出自刷新 模式，以及缓冲器控制单元，被配置为当所述时钟使能信号被去激活时禁用所述多个命令缓冲器，并且当所述刷新控制单元退出所述自刷新模式时启用所述多个命令缓冲器。

公开(公告)号：US20140003174A1

公开(公告)日：2014-01-02

申请号：US13720191

申请日：2012-12-19

Applicant: SK HYNIX INC.

Inventor： Choung-Ki SONG

IPC: G01R31/04 ,  G11C29/00

CPC classification number: G01R31/041 ,  G01R31/046 ,  G11C29/00 ,  G11C29/1201 ,  G11C29/48

Abstract: An integrated circuit chip includes a plurality of test input pads configured to receive a plurality of test input signals, a plurality of single-ended type buffers configured to receive signals input to the plurality of test input pads in a connectivity test mode, a plurality of differential-type buffers configured to receive signals input to the plurality of test input pads in a normal mode, a signal combination unit configured to combine the plurality of test input signals input through the plurality of single-ended type buffers, and to generate a plurality of test output signals, and a plurality of test output pads configured to output the plurality of test output signals in the connectivity test mode.

Abstract translation: 集成电路芯片包括被配置为接收多个测试输入信号的多个测试输入焊盘，多个单端型缓冲器，被配置为在连接测试模式下接收输入到多个测试输入焊盘的信号，多个 差分型缓冲器，其被配置为以正常模式接收输入到所述多个测试输入焊盘的信号;信号组合单元，被配置为组合通过所述多个单端型缓冲器输入的所述多个测试输入信号，并且生成多个 的测试输出信号，以及多个测试输出焊盘，被配置为在连接测试模式下输出多个测试输出信号。

公开(公告)号：US20140002164A1

公开(公告)日：2014-01-02

申请号：US13716816

申请日：2012-12-17

Applicant: SK HYNIX INC.

Inventor： Choung-Ki SONG

IPC: H03H11/26

CPC classification number: H03H11/26 ,  H03K5/133 ,  H03K2005/00241

Abstract: A delay circuit includes a delay unit configured to generate a delayed transmission signal by delaying a transmission signal activated when a first signal or a second signal is activated, a signal type storing unit configured to store whether the first signal and the second signal is activated, and a transmitting unit configured to transmits the delayed transmission signal as a first delayed signal or a second delayed signal in response to a value stored in the signal type storing unit.

Abstract translation: 延迟电路包括：延迟单元，被配置为通过延迟在第一信号或第二信号被激活时激活的传输信号来产生延迟的传输信号;信号类型存储单元，被配置为存储第一信号和第二信号是否被激活; 以及发送单元，被配置为响应于存储在信号类型存储单元中的值，将延迟的发送信号作为第一延迟信号或第二延迟信号进行发送。

公开(公告)号：US20160300611A1

公开(公告)日：2016-10-13

申请号：US15183395

申请日：2016-06-15

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C14/00 ,  G11C5/14 ,  G11C11/406

CPC classification number: G11C14/0018 ,  G11C5/141 ,  G11C11/005 ,  G11C11/40615 ,  G11C11/4072 ,  G11C14/0009

Abstract: A memory module includes an emergency power supplier, a plurality of ranks each including one or more volatile memories, a non-volatile memory, and a controller suitable for backing up data of the ranks into the non-volatile memory by using the emergency power supplier during a power failure, wherein the ranks are sequentially backed up, and while one rank is backed up among the ranks, the other ranks are controlled in a self-refresh mode.

公开(公告)号：US20160148668A1

公开(公告)日：2016-05-26

申请号：US15009388

申请日：2016-01-28

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C11/402

CPC classification number: G11C11/402 ,  G11C7/02 ,  G11C7/20 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4096 ,  G11C2211/4065

Abstract: A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of second memory cells which are connected to a corresponding word line stores the number of activations for the corresponding word line, and an activation number update unit configured to update a value stored in the corresponding group of the plurality of second memory cells connected to the activated word line of the plurality of word lines.

Abstract translation: 存储器包括被配置为包括连接到多个字线的多个第一存储器单元的第一单元阵列，被配置为包括连接到所述多个字线的多个第二存储单元的第二单元阵列，其中， 连接到对应字线的多个第二存储单元存储对应字线的激活次数，以及激活号码更新单元，被配置为更新存储在连接到所述多个第二存储器单元的对应组中的值 激活的多个字线的字线。

公开(公告)号：US20150371691A1

公开(公告)日：2015-12-24

申请号：US14523528

申请日：2014-10-24

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/1084 ,  G11C11/401 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C2207/105 ,  G11C2207/2254

Abstract: A semiconductor device may include: a plurality of data pads; a plurality of data buffers each suitable for buffering a signal inputted through a first input node using a voltage inputted through a second input node, and outputting the buffered signal; and a calibration control unit suitable for generating a test signal in a calibration mode, adjusting the level of the test signal, receiving outputs of the plurality of data buffers while adjusting the level of the test signal, and adjusting offsets of the data buffers such that the logical values of the outputs of the data buffers transit when the test signal has a target level.

Abstract translation: 半导体器件可以包括：多个数据焊盘; 多个数据缓冲器，每个数据缓冲器适于通过使用通过第二输入节点输入的电压缓冲通过第一输入节点输入的信号，并输出缓冲的信号; 以及校准控制单元，其适于在校准模式中生成测试信号，调整测试信号的电平，在调整测试信号的电平的同时接收多个数据缓冲器的输出，以及调整数据缓冲器的偏移量，使得 当测试信号具有目标电平时，数据缓冲器的输出的逻辑值就会转移。

公开(公告)号：US20150255168A1

公开(公告)日：2015-09-10

申请号：US14491754

申请日：2014-09-19

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C17/16 ,  G11C17/18 ,  G11C11/406

CPC classification number: G11C17/16 ,  G06F13/1636 ,  G11C11/40611 ,  G11C17/18 ,  G11C29/78 ,  G11C29/783

Abstract: A semiconductor memory device includes a command buffering unit suitable for receiving and buffering a command signal based on an enable control signal, a fuse array suitable for programming data based on the command signal, and an enable control unit suitable for generating the enable control signal, wherein an activation operation on the command buffering unit by the enable control signal is controlled during a programming operation period of the fuse array.

Abstract translation: 半导体存储器件包括：命令缓冲单元，其适于基于使能控制信号接收和缓冲命令信号，适用于基于命令信号编程数据的熔丝阵列;以及适用于产生使能控制信号的使能控制单元， 其中在所述保险丝阵列的编程操作期间控制由所述使能控制信号对所述命令缓冲单元的激活操作。

公开(公告)号：US20150255132A1

公开(公告)日：2015-09-10

申请号：US14340333

申请日：2014-07-24

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C8/18

CPC classification number: G11C7/1045 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/20 ,  G11C7/22

Abstract: A semiconductor system includes multiple semiconductor devices operating commonly in response to a command signal, wherein each of the multiple semiconductor devices is independently activated according to each of multiple data strobe signals respectively corresponding to the multiple semiconductor devices; and a controller suitable for providing the command signal and the multiple data strobe signals.

Abstract translation: 半导体系统包括响应于命令信号共同工作的多个半导体器件，其中根据分别对应于多个半导体器件的多个数据选通信号中的每一个独立地激活多个半导体器件中的每一个; 以及适于提供命令信号和多个数据选通信号的控制器。

公开(公告)号：US20150235693A1

公开(公告)日：2015-08-20

申请号：US14319896

申请日：2014-06-30

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G06F13/1636 ,  G11C7/02 ,  G11C11/40615

Abstract: A memory system includes a memory module including a plurality of memories and a memory controller suitable for controlling an operation timing of each of the memories, wherein the memories enter a refresh operation mode simultaneously in response to a refresh operation command of the memory controller and individually perform a refresh operation according to the operation timing.

Abstract translation: 存储器系统包括存储器模块，其包括多个存储器和适于控制每个存储器的操作定时的存储器控​​制器，其中存储器响应于存储器控制器的刷新操作命令并且单独地进入刷新操作模式 根据操作时机执行刷新操作。