公开(公告)号：US10360157B2

公开(公告)日：2019-07-23

申请号：US15597866

申请日：2017-05-17

Applicant: SK hynix Inc.

Inventor： Dong-Gun Kim ,  Yong-Ju Kim ,  Sang-Gu Jo ,  Do-Sun Hong

IPC: G06F12/1027 ,  G06F12/1009

Abstract: A memory system includes a memory device including a memory block, the memory block including a plurality of memory cell groups, an address translator that maps a logical address of a data to a physical address of the memory block, and a controller configured to divide the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group, and control the address translator so that the address translator maps a logical address of a data to a physical address of the first memory cell groups of the memory block and not in the at least one second memory cell group and switches the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses.

公开(公告)号：US10083120B2

公开(公告)日：2018-09-25

申请号：US15598401

申请日：2017-05-18

Applicant: SK hynix Inc.

Inventor： Dong-Gun Kim ,  Yong-Ju Kim ,  Sang-Gu Jo ,  Do-Sun Hong

IPC: G06F12/12 ,  G06F12/10 ,  G06F3/06

CPC classification number: G06F12/10 ,  G06F3/061 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0673 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/657 ,  G06F2212/7211

Abstract: Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value; mapping the logical address to a first physical address identical to an interval value when the logical address is identical to the round value; mapping the logical address to a second physical address corresponding to a value obtained by subtracting the round value from the logical address when the logical address is different from the round value; and adjusting a mapping value of the logical address to the second physical address to a value obtained by subtracting one from the second physical address when the second physical address is less than or equal to the interval value.

公开(公告)号：US10019197B2

公开(公告)日：2018-07-10

申请号：US14996407

申请日：2016-01-15

Applicant: SK hynix Inc.

Inventor： Kyung-Min Lee ,  Yong-Ju Kim

IPC: G06F3/06

CPC classification number: G06F12/08

Abstract: A semiconductor system may include: a command queue suitable for storing a plurality of requests provided from a host according to rank and bank information of the requests; one or more determination units suitable for determining requests having a same row address in response to row address information of the requests stored in the command queue; an arbitration unit suitable for scheduling the plurality of requests according to internal priorities of the requests; a monitoring unit suitable for providing the rank information and row hit information of the plurality of requests outputted according to the scheduling result of the arbitration unit, to the arbitration unit; a command generation unit suitable for generating a plurality of commands corresponding to and in response to the plurality of requests outputted according to the scheduling result of the arbitration unit; and a semiconductor memory device suitable for performing an internal operation in response to the command, wherein the arbitration unit reschedules the plurality of requests in response to a monitoring result of the monitoring unit and output results of the plurality of determination units, such that all requests inputted during a preset period are processed.

公开(公告)号：US09225316B2

公开(公告)日：2015-12-29

申请号：US14668488

申请日：2015-03-25

Applicant: SK hynix Inc.

Inventor： Shin-Deok Kang ,  Jae-Min Jang ,  Yong-Ju Kim ,  Hae-Rang Choi

IPC: H03K3/017 ,  H03K5/156

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

公开(公告)号：US08461878B2

公开(公告)日：2013-06-11

申请号：US13680239

申请日：2012-11-19

Applicant: SK Hynix Inc.

Inventor： Ji-Wang Lee ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Jae-Min Jang ,  Chang-Kun Park

IPC: H03K5/153

CPC classification number: H03K5/153

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。