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    Memory system and error correcting method thereof
    1.
    发明授权
    Memory system and error correcting method thereof 有权

    公开(公告)号：US10795763B2

    公开(公告)日：2020-10-06

    申请号：US16203862

    申请日：2018-11-29

    Applicant: SK hynix Inc.

    Inventor： Yong-Ju Kim ,  Do-Sun Hong ,  Dong-Gun Kim

    IPC: G11C29/52 ,  G06F11/10 ,  G11C29/44 ,  G11C29/42 ,  H03M13/15 ,  G11C29/04

    Abstract: A memory system includes a plurality of memory chips suitable for storing data and an error correction code thereof, an error correction circuit suitable for detecting and correcting error bits of data, which are read from the plurality of memory chips, based on an error correction code of the read data, an address storage circuit suitable for storing addresses of first data, among the read data, the first data having a number of detected error bits greater than or equal to a first number, and a failed chip detection circuit suitable for, when the number of the stored addresses is greater than or equal to a second number, detecting a failed memory chip where a chip-kill occurs by writing test data in the plurality of memory chips and reading back the written test data.

    Semiconductor device and operating method thereof
    4.
    发明授权
    Semiconductor device and operating method thereof 有权
    半导体器件及其操作方法

    公开(公告)号：US09477593B2

    公开(公告)日：2016-10-25

    申请号：US14504746

    申请日：2014-10-02

    Applicant: SK hynix Inc.

    Inventor： Dong-Gun Kim ,  Yong-Kee Kwon ,  Hong-Sik Kim

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F2212/7211

    Abstract: A semiconductor device remaps the relationship between logical addresses and physical addresses of a semiconductor memory device at each first interval. The semiconductor device may include a wear leveling controller configured to select a first physical address of the semiconductor memory device to remap a logical address corresponding to the first physical address of the semiconductor memory device to a second physical address of the semiconductor memory device, and to adjust the first interval.

    Abstract translation: 半导体器件在每个第一间隔重新映射半导体存储器件的逻辑地址和物理地址之间的关系。 半导体器件可以包括：磨损均衡控制器，被配置为选择半导体存储器件的第一物理地址，以将对应于半导体存储器件的第一物理地址的逻辑地址重新映射到半导体存储器件的第二物理地址;以及 调整第一个间隔。

    Memory system and operating method thereof
    5.
    发明授权
    Memory system and operating method thereof 有权

    公开(公告)号：US10445005B2

    公开(公告)日：2019-10-15

    申请号：US15726460

    申请日：2017-10-06

    Applicant: SK hynix Inc.

    Inventor： Do-Sun Hong ,  Yong-Ju Kim ,  Dong-Gun Kim

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

    Abstract: A memory system includes a wear-leveling module detecting a hot memory block among a plurality of memory blocks based on the number of times write operations are performed on each of the memory blocks, and moving data from the hot memory block to a spare memory block, a counting unit counting the number of data movement from the hot memory block to the spare memory block, on each of memory regions formed by grouping the plurality of memory blocks, and output data movement counts, a first detection unit selecting one from the plurality of memory regions based on the data movement count, and detecting a cold memory block among memory blocks included in the selected memory region, and a management unit moving data from the cold memory block to the hot memory block, and managing the cold memory block as the spare memory block.

    Memory system and method for wear-leveling by swapping memory cell groups
    7.
    发明授权
    Memory system and method for wear-leveling by swapping memory cell groups 有权

    公开(公告)号：US10360157B2

    公开(公告)日：2019-07-23

    申请号：US15597866

    申请日：2017-05-17

    Applicant: SK hynix Inc.

    Inventor： Dong-Gun Kim ,  Yong-Ju Kim ,  Sang-Gu Jo ,  Do-Sun Hong

    IPC: G06F12/1027 ,  G06F12/1009

    Abstract: A memory system includes a memory device including a memory block, the memory block including a plurality of memory cell groups, an address translator that maps a logical address of a data to a physical address of the memory block, and a controller configured to divide the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group, and control the address translator so that the address translator maps a logical address of a data to a physical address of the first memory cell groups of the memory block and not in the at least one second memory cell group and switches the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses.

    Memory system and wear-leveling method thereof
    9.
    发明授权
    Memory system and wear-leveling method thereof 有权

    公开(公告)号：US09990153B2

    公开(公告)日：2018-06-05

    申请号：US15618597

    申请日：2017-06-09

    Applicant: SK hynix Inc.

    Inventor： Jung-Hyun Kwon ,  Dong-Gun Kim ,  Sang-Gu Jo

    IPC: G06F12/02 ,  G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7211

    Abstract: A memory system includes a memory device performing write operations on lines included in a memory block among a plurality of memory blocks included in the memory device; a counting unit counting a write count for each of the plurality of memory blocks, and outputting the write counts; a first wear-leveling unit performing a wear leveling operation by shifting the lines of each of the plurality of memory blocks; and a second wear-leveling unit detecting hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swapping the hot memory block with the cold memory block, wherein the second wear-leveling unit selects at least one memory block among the plurality of memory blocks based on the write counts, and checks whether the write operation is performed on each of the lines included in the selected memory block.

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09524124B2

    公开(公告)日：2016-12-20

    申请号：US14523363

    申请日：2014-10-24

    Applicant: SK hynix Inc.

    Inventor： Dong-Gun Kim ,  Yong-Kee Kwon ,  Hong-Sik Kim

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0688 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0638 ,  G06F3/0644 ,  G06F3/0679

    Abstract: A semiconductor device may include a first memory cell array configured to store data according to a first address on a first basis, a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis, a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request, and an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array.

    Abstract translation: 半导体器件可以包括第一存储器单元阵列，其被配置为在第一基础上存储根据第一地址的数据;第二存储单元阵列，被配置为根据第二地址在第二基础上存储数据，该第二地址相对小于第一基础 配置为在写入请求期间选择第一存储单元阵列和第二存储单元阵列之一以存储数据的存储器选择器，以及地址映射表，被配置为在第一和第二地址之间存储映射信息，以存储在第二存储单元阵列 存储单元阵列。

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