公开(公告)号：US20160268430A1

公开(公告)日：2016-09-15

申请号：US15161994

申请日：2016-05-23

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/165 ,  H01L27/12 ,  H01L29/08 ,  H01L29/161 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

Abstract translation: 形成半导体结构的方法包括提供具有覆盖在掩埋氧化物层上方的应变初级半导体层的外延基底层的多层衬底。 外延基底层内的元素用于改变多层基底的第一区域内的初级半导体层中的应变状态，而不改变多层基底的第二区域内的初级半导体层中的应变状态。 形成第一多个晶体管沟道结构，每个晶体管沟道结构各自包括多层衬底的第一区域内的初级半导体层的一部分，并且形成第二多个晶体管沟道结构，每个晶体管沟道结构各自包括初级半导体层的一部分 在多层基板的第二区域内。 通过这种方法制造的半导体结构可以包括具有不同应变状态的晶体管沟道结构。

公开(公告)号：US20160087100A1

公开(公告)日：2016-03-24

申请号：US14938545

申请日：2015-11-11

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/165 ,  H01L27/12

CPC classification number: H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

公开(公告)号：US20140369646A1

公开(公告)日：2014-12-18

申请号：US14474503

申请日：2014-09-02

Applicant: SOITEC

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka

IPC: H01L25/16 ,  H01L33/34 ,  G02B6/12 ,  H01L27/12

CPC classification number: H01L25/167 ,  G02B6/12002 ,  G02B6/12004 ,  H01L27/0688 ,  H01L27/1203 ,  H01L31/103 ,  H01L33/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling a waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.

Abstract translation: 三维集成半导体系统包括在绝缘体上半导体（SeOI）衬底上与电流/电压转换器可操作地耦合的光活性器件。 光学互连可操作地耦合到光活性器件。 半导体器件接合在SeOI衬底上，并且电路在电流/电压转换器和接合在SeOI衬底上的半导体器件之间延伸。 形成这种系统的方法包括在SeOI衬底上形成光活性器件，并且可操作地将波导与光活性器件耦合。 可以在SeOI衬底上形成电流/电压转换器，并且光敏器件和电流/电压转换器可以彼此可操作地耦合。 半导体器件可以接合在SeOI衬底上并且与电流/电压转换器可操作地耦合。