公开(公告)号：US20200331750A1

公开(公告)日：2020-10-22

申请号：US16921675

申请日：2020-07-06

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ludovic Ecarnot

IPC: B81C1/00 ,  B81B1/00

Abstract: Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.

公开(公告)号：US20170210617A1

公开(公告)日：2017-07-27

申请号：US15328371

申请日：2014-06-11

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ludovic Ecarnot

IPC: B81C1/00 ,  B81B1/00

Abstract: Methods of forming semiconductor structures comprising one or more cavities (106), which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate (100), providing a sacrificial material (110) within the one or more cavities, bonding a second substrate (120) over the a surface of the first substrate, forming one or more apertures (140) through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.

公开(公告)号：US09511996B2

公开(公告)日：2016-12-06

申请号：US14416860

申请日：2013-07-08

Applicant: Soitec

Inventor： Mariam Sadaka ,  Bernard Aspar ,  Chrystelle Lagahe Blanchard

IPC: H01L27/14 ,  B81C1/00 ,  H03H9/10 ,  B81B7/00

CPC classification number: B81C1/00246 ,  B81B7/0006 ,  B81B2201/0271 ,  B81B2207/015 ,  B81C1/00238 ,  B81C2203/0735 ,  B81C2203/0792 ,  H03H9/10

Abstract: Methods are used to form semiconductor devices that include an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit. At least a portion of an integrated circuit may be fabricated on a surface of a substrate, and a MEMS device may be formed over the at least a portion of the integrated circuit. The MEMS device may be operatively coupled with the integrated circuit. Semiconductor structures and electronic devices including such structures are formed using such methods.

Abstract translation: 方法用于形成半导体器件，其包括集成电路和与集成电路可操作地耦合的微机电系统（MEMS）器件。 可以在衬底的表面上制造集成电路的至少一部分，并且可以在集成电路的至少一部分上形成MEMS器件。 MEMS器件可以与集成电路可操作地耦合。 使用这种方法形成包括这种结构的半导体结构和电子器件。

公开(公告)号：US09481566B2

公开(公告)日：2016-11-01

申请号：US14416825

申请日：2013-07-08

Applicant: Soitec

Inventor： Mariam Sadaka ,  Bernard Aspar ,  Chrystelle Lagahe Blanchard

IPC: H01L29/40 ,  B81B7/00 ,  B81C1/00 ,  H03H9/10

CPC classification number: B81B7/007 ,  B81B2201/0271 ,  B81B2207/012 ,  B81B2207/015 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00301 ,  B81C2203/0735 ,  B81C2203/0792 ,  H01L2224/16 ,  H03H9/10

Abstract: Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.

Abstract translation: 形成包括集成电路的半导体器件和与集成电路可操作耦合的微机电系统（MEMS）器件的方法包括形成导电通孔，该导电通孔至少部分地穿过衬底，从衬底的第一主表面向相对的第二主表面延伸 的衬底，以及在衬底的第一主表面上制造集成电路的至少一部分。 MEMS器件设置在衬底的第二主表面上，并且MEMS器件使用至少一个导电通孔与集成电路操作耦合。 使用这种方法制造结构和装置。

公开(公告)号：US09293448B2

公开(公告)日：2016-03-22

申请号：US14474503

申请日：2014-09-02

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka

IPC: G02B6/12 ,  H01L25/16 ,  H01L31/103 ,  H01L27/06 ,  H01L27/12 ,  H01L33/34

CPC classification number: H01L25/167 ,  G02B6/12002 ,  G02B6/12004 ,  H01L27/0688 ,  H01L27/1203 ,  H01L31/103 ,  H01L33/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling a waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.

Abstract translation: 三维集成半导体系统包括在绝缘体上半导体（SeOI）衬底上与电流/电压转换器可操作地耦合的光活性器件。 光学互连可操作地耦合到光活性器件。 半导体器件接合在SeOI衬底上，并且电路在电流/电压转换器和接合在SeOI衬底上的半导体器件之间延伸。 形成这种系统的方法包括在SeOI衬底上形成光活性器件，并且可操作地将波导与光活性器件耦合。 可以在SeOI衬底上形成电流/电压转换器，并且光敏器件和电流/电压转换器可以彼此可操作地耦合。 半导体器件可以接合在SeOI衬底上并且与电流/电压转换器可操作地耦合。

公开(公告)号：US09219150B1

公开(公告)日：2015-12-22

申请号：US14489817

申请日：2014-09-18

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC: H01L23/52 ,  H01L21/8238 ,  H01L21/30 ,  H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L21/306 ,  H01L21/265 ,  H01L21/22 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

Abstract translation: 形成半导体结构的方法包括提供具有覆盖在掩埋氧化物层上方的应变初级半导体层的外延基底层的多层衬底。 外延基底层内的元素用于改变多层基底的第一区域内的初级半导体层中的应变状态，而不改变多层基底的第二区域内的初级半导体层中的应变状态。 形成第一多个晶体管沟道结构，每个晶体管沟道结构各自包括多层衬底的第一区域内的初级半导体层的一部分，并且形成第二多个晶体管沟道结构，每个晶体管沟道结构各自包括初级半导体层的一部分 在多层基板的第二区域内。 通过这种方法制造的半导体结构可以包括具有不同应变状态的晶体管沟道结构。

公开(公告)号：US20150179639A1

公开(公告)日：2015-06-25

申请号：US14642196

申请日：2015-03-09

Applicant: Soitec

Inventor： Mariam Sadaka

IPC: H01L27/06 ,  H01L23/367 ,  H01L23/46 ,  H01L27/12

CPC classification number: H01L23/49827 ,  B01L3/502707 ,  B01L2300/0864 ,  B01L2300/0867 ,  B01L2300/0874 ,  B01L2300/0887 ,  H01L21/2007 ,  H01L23/367 ,  H01L23/46 ,  H01L23/473 ,  H01L23/49822 ,  H01L24/14 ,  H01L24/16 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2224/13011 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17519 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/12041 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.

Abstract translation: 制造半导体结构，其包括在半导体材料和衬底之间具有电介质材料层的衬底上结合的半导体材料。 至少一个流体微通道在横向方向上延伸穿过半导体材料和衬底之间的介电材料层。 所述至少一个流体微通道包括至少一个横向延伸部分，其横截面形状完全由电介质材料层包围。

公开(公告)号：US08637995B2

公开(公告)日：2014-01-28

申请号：US13657327

申请日：2012-10-22

Applicant: Soitec ,  Mariam Sadaka

Inventor： Mariam Sadaka

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/76254 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/481 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/80097 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00

Abstract: Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are foamed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.

Abstract translation: 形成半导体器件的方法包括在电绝缘材料层上提供包括半导体材料层的衬底。 第一金属化层形成在半导体材料层的第一侧上。 通过晶片互连件至少部分地通过衬底发泡。 第二金属化层形成在半导体材料层的与其第一侧相对的第二侧上。 提供了一种电路，其通过第一金属化层，衬底和第二金属化层延伸，所述第一金属化层和第二金属化层位于由半导体材料层的第一侧上的衬底承载的第一处理半导体结构和由第 衬底在半导体材料层的第一侧上。 使用这种方法制造半导体结构。

公开(公告)号：US20130299997A1

公开(公告)日：2013-11-14

申请号：US13937779

申请日：2013-07-09

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2221/6839 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0381 ,  H01L2224/05009 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08146 ,  H01L2224/80006 ,  H01L2224/80065 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/80 ,  H01L2924/00

Abstract: Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.

Abstract translation: 形成键合的半导体结构的方法包括暂时将半导体结构直接结合在一起，使半导体结构中的至少一个变薄，然后将稀化的半导体结构永久地结合到另一个半导体结构。 可以在不使用粘合剂的情况下建立临时的直接粘合。 结合的半导体结构根据这样的方法制造。

公开(公告)号：US20130256907A1

公开(公告)日：2013-10-03

申请号：US13900157

申请日：2013-05-22

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/98 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/0903 ,  H01L2224/16145 ,  H01L2224/27444 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80 ,  H01L2224/80006 ,  H01L2224/80011 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80805 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3512

Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.