公开(公告)号：US20250081561A1

公开(公告)日：2025-03-06

申请号：US18952033

申请日：2024-11-19

Applicant: Soitec ,  National University of Singapore

Inventor： Bich-Yen Nguyen ,  Christophe Maleville ,  Walter Schwarzenbach ,  Gong Xiao ,  Aaron Thean ,  Chen Sun ,  Haiwen Xu

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/265 ,  H01L21/84 ,  H01L27/10 ,  H01L27/12 ,  H01L29/161 ,  H01L29/78

Abstract: A method of preparing a semiconductor structure includes forming an insulating layer having a thickness between about 5 nm and about 100 nm on a substrate, and forming an active layer comprising a tensile-strained silicon over the insulating layer. At least a portion of the active layer is implanted with ions to render at least a portion of the active layer amorphous and reduce the tensile strain in the at least portion of the active layer. The method further includes thermally annealing the implanted portion of the active layer and recrystallizing such previously rendered amorphous portion of the active layer. A germanium condensation process is performed on the recrystallized portion of the active layer to form a SiGe material having a compressive strain. Also described are the semiconductor structures.

公开(公告)号：US20240145314A1

公开(公告)日：2024-05-02

申请号：US18402215

申请日：2024-01-02

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/8238 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/3247 ,  H01L21/7624

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

公开(公告)号：US09576798B2

公开(公告)日：2017-02-21

申请号：US14934567

申请日：2015-11-06

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Christophe Maleville

IPC: H01L21/8238 ,  H01L27/12 ,  H01L21/266 ,  H01L21/336 ,  H01L21/225 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L21/84 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L21/2253 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/76251 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/32 ,  H01L29/7849

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括提供包括基底基板，在基底基板上方的应变应力层，表面半导体层和应力层与表面半导体层之间的电介质层的绝缘体上半导体 。 离子被注入或穿过应力层的第一区域，并且在应力层的第一区域上方的表面半导体层上形成附加的半导体材料。 在应力层的第一区域上方的表面半导体层的第一区域中的应变状态被改变，并且沟槽结构至少部分地形成到基底衬底中。 在应力层的第二区域上方的表面半导体层的第二区域中改变应变状态。 使用这种方法制造半导体结构。

公开(公告)号：US20160372484A1

公开(公告)日：2016-12-22

申请号：US15176925

申请日：2016-06-08

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Frederic Allibert ,  Christophe Maleville

IPC: H01L27/12 ,  H01L21/266 ,  H01L21/84 ,  H01L23/66

CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/84 ,  H01L23/66

Abstract: A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency, RF, circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.

Abstract translation: 一种用于制造绝缘体上绝缘体上的高电阻半导体衬底的方法，包括以下步骤：a）在高电阻率衬底上形成电介质层和半导体层，使得电介质层布置在高电阻率衬底和 半导体层; b）在所述半导体层上形成硬掩模或抗蚀剂，其中所述硬掩模或抗蚀剂在预定位置具有至少一个开口; c）通过所述硬掩模或抗蚀剂，所述半导体层和所述电介质层的所述至少一个开口离子注入杂质元素，在所述高电阻率衬底中形成至少一个掺杂区域; d）去除硬掩模或抗蚀剂; 以及e）在所述半导体层中和/或之上形成至少部分地与所述高电阻率衬底中的所述至少一个掺杂区域重叠的射频RF电路。

公开(公告)号：US09293448B2

公开(公告)日：2016-03-22

申请号：US14474503

申请日：2014-09-02

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka

IPC: G02B6/12 ,  H01L25/16 ,  H01L31/103 ,  H01L27/06 ,  H01L27/12 ,  H01L33/34

CPC classification number: H01L25/167 ,  G02B6/12002 ,  G02B6/12004 ,  H01L27/0688 ,  H01L27/1203 ,  H01L31/103 ,  H01L33/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling a waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.

Abstract translation: 三维集成半导体系统包括在绝缘体上半导体（SeOI）衬底上与电流/电压转换器可操作地耦合的光活性器件。 光学互连可操作地耦合到光活性器件。 半导体器件接合在SeOI衬底上，并且电路在电流/电压转换器和接合在SeOI衬底上的半导体器件之间延伸。 形成这种系统的方法包括在SeOI衬底上形成光活性器件，并且可操作地将波导与光活性器件耦合。 可以在SeOI衬底上形成电流/电压转换器，并且光敏器件和电流/电压转换器可以彼此可操作地耦合。 半导体器件可以接合在SeOI衬底上并且与电流/电压转换器可操作地耦合。

公开(公告)号：US09219150B1

公开(公告)日：2015-12-22

申请号：US14489817

申请日：2014-09-18

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC: H01L23/52 ,  H01L21/8238 ,  H01L21/30 ,  H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L21/306 ,  H01L21/265 ,  H01L21/22 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

Abstract translation: 形成半导体结构的方法包括提供具有覆盖在掩埋氧化物层上方的应变初级半导体层的外延基底层的多层衬底。 外延基底层内的元素用于改变多层基底的第一区域内的初级半导体层中的应变状态，而不改变多层基底的第二区域内的初级半导体层中的应变状态。 形成第一多个晶体管沟道结构，每个晶体管沟道结构各自包括多层衬底的第一区域内的初级半导体层的一部分，并且形成第二多个晶体管沟道结构，每个晶体管沟道结构各自包括初级半导体层的一部分 在多层基板的第二区域内。 通过这种方法制造的半导体结构可以包括具有不同应变状态的晶体管沟道结构。

公开(公告)号：US08625374B2

公开(公告)日：2014-01-07

申请号：US13718571

申请日：2012-12-18

Applicant: Soitec

Inventor： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC: G11C7/00 ,  G11C11/4091

CPC classification number: G11C7/08 ,  G11C7/06 ,  G11C7/067 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2211/4016

Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.

Abstract translation: 一种用于存储器的一系列单元的读出放大器，包括一个写入级，它包括一个CMOS反相器，其输入直接或间接地连接到读出放大器的输入端，并且其输出端连接到输出端 所述读出放大器旨在连接到寻址该串联的单元的本地位线;以及读取级，其包括检测晶体管，其栅极连接到反相器的输出端，其漏极连接到 输入变频器。

公开(公告)号：US20230170264A1

公开(公告)日：2023-06-01

申请号：US17995791

申请日：2021-03-29

Applicant: Soitec

Inventor： Trong Hyunh-Bao ,  Bich-Yen Nguyen ,  Christophe Maleville

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/42376 ,  H01L21/76281

Abstract: A method for manufacturing a semiconductor-on-insulator (SeOI) chip comprises: a) providing a SeOI structure, b) building a plurality of isolated field effect transistors (FET) each comprising: —a preliminary gate above a channel region, the FETs from a first group having a first preliminary gate length and the FETs from a second group having a smaller second preliminary gate length, —a source region and a drain region, and —a source electrode and a drain electrode, c) removing at least the preliminary gates of the FETs from the second group, leaving access to channel regions of the FETs, d) thinning a top layer in channel regions of the FETs from the second group, the top layer in channel regions of the first group of FETs having a different thickness, and e) forming functional gates simultaneously on channel regions of the FETs whose preliminary gates were removed.

公开(公告)号：US20230129131A1

公开(公告)日：2023-04-27

申请号：US17452197

申请日：2021-10-25

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Gweltaz Gaudin

IPC: G02B6/132 ,  G02B6/136 ,  H01L21/762

Abstract: A method for manufacturing a semiconductor structure or a photonic device, wherein the method comprises the steps of: providing a silicon nitride patterned layer over a carrier substrate; providing a first layer of a conformal oxide on the silicon nitride patterned layer such that it fully covers the silicon nitride patterned layer; and planarizing the first layer of conformal oxide to a predetermined thickness above the silicon nitride patterned layer to form a planarizing oxide layer. After the step of planarizing the first layer of conformal oxide, the method further comprises steps of clearing the silicon nitride patterned layer to form a dished silicon nitride patterned layer with a dishing height; and subsequently providing a second layer of a conformal oxide on or over the dished silicon nitride layer.

公开(公告)号：US20220076992A1

公开(公告)日：2022-03-10

申请号：US17417715

申请日：2019-12-23

Applicant: Soitec

Inventor： Yvan Morandini ,  Walter Schwarzenbach ,  Frédéric Allibert ,  Eric Desbonnets ,  Bich-Yen Nguyen

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/322 ,  H01L27/12 ,  H01L29/06

Abstract: A semiconductor-on-insulator multilayer structure, comprises: —a stack, called the back stack, of the following layers from a back side to a front side of the structure: a semiconductor carrier substrate the electrical resistivity of which is between 500 Ω·cm and 30 kΩ·cm, a first electrically insulating layer, a first semiconductor layer, —at least one trench isolation that extends through the back stack at least down to the first electrically insulating layer), and that electrically isolates two adjacent regions of the multilayer structure, the multilayer structure being characterized in that it further comprises at least one FD-SOI first region, and at least one RF-SOI second region.