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公开(公告)号：US20220399880A1
公开(公告)日：2022-12-15
申请号：US17830864
申请日：2022-06-02
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Antonino Conte , Marco Ruta , Michelangelo Pisasale , Thomas Jouanneau
Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.
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公开(公告)号：US20220284954A1
公开(公告)日：2022-09-08
申请号：US17667080
申请日：2022-02-08
Inventor： Antonino Conte , Alin Razafindraibe , Francesco Tomaiuolo , Thibault Mortier
IPC: G11C13/00
Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage configured to decouple from or couple to a node at a first reference potential each wordline that extends through the group of memory portions, when the wordline is respectively selected or deselected, so as to impose on each wordline, when deselected, a deselection voltage, a plurality of pull-down stages distributed along the group of memory portions, each pull-down stage being configured to locally couple each wordline that extends through the group of memory portions, when selected, to a node at a second reference potential, so as to impose locally a selection voltage on the wordline, wherein each pull-down stage is further configured to locally decouple from the node at the second reference potential each wordline that extends through the group of memory portions, when deselected; and a number of local pull-up stages distributed along the group of memory portions, each local pull-up stage having, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type.
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公开(公告)号：US10796758B2
公开(公告)日：2020-10-06
申请号：US16299226
申请日：2019-03-12
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte
Abstract: Described herein is a non-volatile memory device in which it is possible to switch between different reading modes. In particular, the memory device includes a plurality of memory cells and implements, alternatively, a reading of a differential type and a reading of a single-ended type. Further described herein is a method for reading the memory device.
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公开(公告)号：US10658048B2
公开(公告)日：2020-05-19
申请号：US16104001
申请日：2018-08-16
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte , Loredana Chiaramonte , Anna Rita Maria Lipani
Abstract: A sense structure includes: a sense amplifier core configured to compare a measurement current with a reference current; a cascode transistor coupled to the sense amplifier core and configured to be coupled to a load; a switch coupled between a bias voltage node and a control terminal of the cascode transistor; a local capacitor having a first terminal coupled to the control terminal of the cascode transistor; a first transistor coupled between a second terminal of the local capacitor and a reference terminal; and a control circuit coupled to a control terminal of the first transistor, the control circuit configured to disconnect the local capacitor from the reference terminal to produce a voltage overshoot in the control terminal of the cascode transistor, and after disconnecting the local capacitor from the reference terminal, limit or reduce the voltage overshoot by adjusting a voltage of the control terminal of the first transistor.
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35.发明申请公开(公告)号：US20200126616A1
公开(公告)日：2020-04-23
申请号：US16717652
申请日：2019-12-17
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte
Abstract: A phase-change memory device includes a memory array including a first memory cell and a second memory cell, each comprising a phase-change element and a selector, connected respectively to a first local bitline and a second local bitline, which are in turn connected, respectively, to a first main bitline and a second main bitline. The parasitic capacitance of the main bitlines is precharged at a supply voltage. When the local bitlines are selected to access a respective logic datum stored in the phase-change element, the parasitic capacitance of the local bitlines is first charged using the charge previously stored in the parasitic capacitance of the main bitlines and then discharged through the respective phase-change elements. Reading of the logic datum is made by comparing the discharge times.
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Patent Agency Ranking
公开(公告)号：US10593400B2
公开(公告)日：2020-03-17
申请号：US16222484
申请日：2018-12-17
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte
Abstract: In an embodiment, a non-volatile memory device includes a memory array divided into a plurality of tiles, and a row decoder that includes main row decoding units associated to a respective group of tiles. The row decoded further includes local row decoding units, each associated to a respective tile for carrying out selection and biasing of corresponding word lines based on decoded address signals and biasing signals. Each local row decoding unit has logic-combination modules coupled to a set of word lines and include, for each word line, a pull-down stage for selecting a word line, and a pull-up stage. The pull-up stage is dynamically biased, alternatively, in a strong-biasing condition towards a tile-supply voltage when the word line is not selected, or in a weak-biasing condition when the word line is selected.
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37.发明授权公开(公告)号：US10297292B2
公开(公告)日：2019-05-21
申请号：US15620325
申请日：2017-06-12
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte , Mario Micciche' , Santi Nunzio Antonino Pagano
Abstract: A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascade configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.
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38.发明申请公开(公告)号：US20190096480A1
公开(公告)日：2019-03-28
申请号：US16133097
申请日：2018-09-17
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte
Abstract: A phase-change memory device includes a memory array including a first memory cell and a second memory cell, each comprising a phase-change element and a selector, connected respectively to a first local bitline and a second local bitline, which are in turn connected, respectively, to a first main bitline and a second main bitline. The parasitic capacitance of the main bitlines is precharged at a supply voltage. When the local bitlines are selected to access a respective logic datum stored in the phase-change element, the parasitic capacitance of the local bitlines is first charged using the charge previously stored in the parasitic capacitance of the main bitlines and then discharged through the respective phase-change elements. Reading of the logic datum is made by comparing the discharge times.
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公开(公告)号：US10217503B2
公开(公告)日：2019-02-26
申请号：US16151388
申请日：2018-10-04
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Antonino Conte , Enrico Castaldo , Raul Andres Bianchi , Francesco La Rosa
Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.
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公开(公告)号：US09964976B2
公开(公告)日：2018-05-08
申请号：US15596895
申请日：2017-05-16
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte , Carmelo Paolino
Abstract: A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.
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