公开(公告)号：US20180032430A1

公开(公告)日：2018-02-01

申请号：US15663619

申请日：2017-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Jongmin Gim ,  Hongzhong Zheng

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/023 ,  G06F12/121 ,  G06F13/1668 ,  G06F2212/251

Abstract: A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

公开(公告)号：US12248402B2

公开(公告)日：2025-03-11

申请号：US18070328

申请日：2022-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/0879 ,  G11C11/417

Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

公开(公告)号：US12236239B2

公开(公告)日：2025-02-25

申请号：US18368515

申请日：2023-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Wenqin Huangfu

IPC: G06F9/30 ,  G06F7/53 ,  G06F7/57

Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.

公开(公告)号：US11893239B2

公开(公告)日：2024-02-06

申请号：US16787002

申请日：2020-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G06F15/78 ,  G06F13/42

CPC classification number: G06F3/0611 ,  G06F3/068 ,  G06F3/0659 ,  G06F12/02 ,  G06F13/1615 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7821

Abstract: A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit includes a first interface coupled to a host device and a second interface coupled to the HBM device. The logic circuit receives a first command from the host device through the first interface and converts the received first command to a first processing-in-memory (PIM) command that is sent to the HBM device through the second interface. The first PIM command has a deterministic latency for completion. The logic circuit further receives a second command from the host device through the first interface and converting the received second command to a second PIM command that is sent to the HBM device through the second interface. The second PIM command has a non-deterministic latency for completion.

公开(公告)号：US20240028332A1

公开(公告)日：2024-01-25

申请号：US18375874

申请日：2023-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Peng Gu ,  Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F9/30 ,  G06F12/02 ,  G06F17/16 ,  G06F7/00 ,  G06F7/487

CPC classification number: G06F9/3001 ,  G06F12/0207 ,  G06F17/16 ,  G06F7/00 ,  G06F7/4876 ,  G06F9/3004 ,  G06F2212/1024

Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.

公开(公告)号：US11782707B2

公开(公告)日：2023-10-10

申请号：US17548220

申请日：2021-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi ,  Wenqin Huangfu

IPC: G06F9/30 ,  G06F7/57 ,  G06F7/53

CPC classification number: G06F9/3001 ,  G06F7/5318 ,  G06F7/57 ,  G06F9/3016 ,  G06F9/30036 ,  G06F9/30098

Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.

公开(公告)号：US20230289081A1

公开(公告)日：2023-09-14

申请号：US18315821

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Peng Gu ,  Krishna T. Malladi ,  Hongzhong Zheng

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/064 ,  G06N3/08 ,  G06F3/0673 ,  G06F3/0604

Abstract: A storage device and method of controlling a storage device are disclosed. The storage device includes a host, a logic die, and a high bandwidth memory stack including a memory die. A computation lookup table is stored on a memory array of the memory die. The host sends a command to perform an operation utilizing a kernel and a plurality of input feature maps, includes finding the product of a weight of the kernel and values of multiple input feature maps. The computation lookup table includes a row corresponding to a weight of the kernel, and a column corresponding to a value of the input feature maps. A result value stored at a position corresponding to a row and a column is the product of the weight corresponding to the row and the value corresponding to the column.

公开(公告)号：US11556476B2

公开(公告)日：2023-01-17

申请号：US17121488

申请日：2020-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien Chang ,  Krishna T. Malladi ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/0875 ,  G06F13/16 ,  G06F13/12 ,  G06F9/30

Abstract: A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

公开(公告)号：US20220413750A1

公开(公告)日：2022-12-29

申请号：US17898207

申请日：2022-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. Malladi

IPC: G06F3/06

Abstract: A method for in-memory computing. In some embodiments, the method includes: executing, by a first function-in-memory circuit, a first instruction, to produce, as a result, a first value, wherein a first computing task includes a second computing task and a third computing task, the second computing task including the first instruction; storing, by the first function-in-memory circuit, the first value in a first buffer; reading, by a second function-in-memory circuit, the first value from the first buffer; and executing, by a second function-in-memory circuit, a second instruction, the second instruction using the first value as an argument, the third computing task including the second instruction, wherein: the storing, by the first function-in-memory circuit, of the first value in the first buffer includes directly storing the first value in the first buffer.

公开(公告)号：US11513965B2

公开(公告)日：2022-11-29

申请号：US17156362

申请日：2021-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Krishna T. Malladi ,  Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

IPC: G06F12/08 ,  G06F12/0879 ,  G11C11/417

Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.