公开(公告)号：US11972820B2

公开(公告)日：2024-04-30

申请号：US17898850

申请日：2022-08-30

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Dengtao Zhao ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102

Abstract: Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected word line in a selected sub-block with program-verify performed between pulses. Unselected NAND strings are inhibited from programming by boosting channels of the unselected NAND strings in the selected sub-block from a positive pre-charge voltage to a boosted voltage. The pre-charging of the channels of unselected NAND strings is performed while lowering voltages at the end of program-verify by applying overdrive voltages to data word lines in a sub-block closer to the source line than the selected sub-block and lowering to a resting voltage a dummy word line between the sub-blocks prior to lowering to a resting voltage the data word lines in the sub-block closer to the source line.

公开(公告)号：US20240079068A1

公开(公告)日：2024-03-07

申请号：US17939748

申请日：2022-09-07

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta ,  Peng Zhang ,  Heguang Li

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3427 ,  G11C16/10 ,  G11C16/26

Abstract: A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks and the plurality of sub-blocks includes a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines; and control circuitry coupled to the block of N wordlines. The control circuitry is configured to: perform a program operation in a normal order programming sequence on the first sub-block; perform a sensing operation on the first sub-block using a reverse sensing scheme; perform a program operation in a reverse order programming sequence on the second sub-block; and perform a sensing operation on the second sub-block using a regular sensing scheme.

公开(公告)号：US20230197168A1

公开(公告)日：2023-06-22

申请号：US17549457

申请日：2021-12-13

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Dengtao Zhao ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/28 ,  G11C16/10

CPC classification number: G11C16/28 ,  G11C16/10

Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).

公开(公告)号：US20230186996A1

公开(公告)日：2023-06-15

申请号：US17549471

申请日：2021-12-13

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Dengtao Zhao ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C7/04

CPC classification number: G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C7/04

Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).

公开(公告)号：US20230050955A1

公开(公告)日：2023-02-16

申请号：US17399498

申请日：2021-08-11

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Gerrit Jan Hemink ,  Xiang Yang ,  Ken Oowada ,  Guirong Liang

IPC: G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

Abstract: To help reduce program disturbs in non-selected NAND strings of a non-volatile memory, a sub-block based boosting scheme in introduced. For a three dimensional NAND memory structure, in which the memory cells above a joint region form an upper sub-block and memory cells below the joint region form a lower sub-block, dummy word lines in the joint region act as select gates to allow boosting at the sub-block level when the lower block is being programmed in a reverse order.

公开(公告)号：US11568943B2

公开(公告)日：2023-01-31

申请号：US17102954

申请日：2020-11-24

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Dengtao Zhao ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08 ,  G11C16/14

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and are also arranged in strings and configured to retain a threshold voltage within a common range of threshold voltages. A control circuit coupled to the plurality of word lines and the strings is configured to determine an erase upper tail voltage of a distribution of the threshold voltage of the memory cells following an erase operation. The erase upper tail voltage corresponds to a cycling condition of the memory cells. The control circuit is also configured to calculate a program voltage to apply to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells during a program operation based on the erase upper tail voltage.

公开(公告)号：US11557358B2

公开(公告)日：2023-01-17

申请号：US17231071

申请日：2021-04-15

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed after being suspended. The control circuit applies an erase signal having a plurality of voltage segments temporally separated from one another during the erase time period to each of the strings while simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation.

公开(公告)号：US11508440B1

公开(公告)日：2022-11-22

申请号：US17323708

申请日：2021-05-18

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Ravi Kumar ,  Chin-Yi Chen ,  Ryohei Shoji

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11582

Abstract: A nonvolatile memory control method includes a step of writing, repeatedly to a nonvolatile memory cells. The method continues with detecting when writing reaches a writing threshold value. Upon reaching the writing threshold, the method continues with driving a charge to at least one parasitic area intermediate at least two charge storage areas of the nonvolatile memory cells to improve data retention in at least one of the at least two charge storage areas of the nonvolatile memory cells.

公开(公告)号：US20220336029A1

公开(公告)日：2022-10-20

申请号：US17231071

申请日：2021-04-15

Applicant: SanDisk Technologies LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/16

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed after being suspended. The control circuit applies an erase signal having a plurality of voltage segments temporally separated from one another during the erase time period to each of the strings while simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation.

公开(公告)号：US11423993B2

公开(公告)日：2022-08-23

申请号：US16676023

申请日：2019-11-06

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Peng Zhang ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06 ,  G11C16/04

Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.