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    Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same
    32.
    发明申请
    Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same 有权
    具有单晶薄膜晶体管的半导体集成电路器件及其制造方法

    公开(公告)号：US20060102959A1

    公开(公告)日：2006-05-18

    申请号：US11280045

    申请日：2005-11-15

    申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim ,  Kun-Ho Kwak ,  Hoon Lim

    发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Jong-Hyuk Kim ,  Kun-Ho Kwak ,  Hoon Lim

    IPC分类号： H01L29/94

    CPC分类号： H01L27/0688 ,  H01L21/8221

    摘要： Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same are provided. The semiconductor integrated circuit devices include an interlayer insulating layer formed on a semiconductor substrate and a single crystalline semiconductor plug penetrating the interlayer insulating layer. A single crystalline semiconductor body pattern is provided on the interlayer insulating layer. The single crystalline semiconductor body pattern has an elevated region and contacts the single crystalline semiconductor plug. The method of forming the single crystalline semiconductor body pattern having the elevated region includes forming a sacrificial layer pattern covering the single crystalline semiconductor plug on the interlayer insulating layer. A capping layer is formed to cover the sacrificial layer pattern and the interlayer insulating layer, and the capping layer is patterned to form an opening which exposes a portion of the sacrificial layer pattern. Subsequently, the sacrificial layer pattern is selectively removed to form a cavity in the capping layer, and a planarized single crystalline semiconductor body pattern is formed to fill the cavity and the opening.

    摘要翻译： 提供具有单晶薄膜晶体管的半导体集成电路器件及其制造方法。 半导体集成电路器件包括形成在半导体衬底上的层间绝缘层和贯穿层间绝缘层的单晶半导体插件。 在层间绝缘层上设置单晶体半导体图案。 单晶半导体主体图案具有升高的区域并与单晶半导体插头接触。 形成具有升高区域的单晶半导体主体图案的方法包括在层间绝缘层上形成覆盖单晶半导体插塞的牺牲层图案。 形成覆盖牺牲层图案和层间绝缘层的覆盖层，并且对覆盖层进行图案化以形成露出牺牲层图案的一部分的开口。 随后，选择性地去除牺牲层图案以在封盖层中形成空腔，并且形成平坦化的单晶半导体主体图案以填充空腔和开口。

    SRAM cells having landing pad in contact with upper and lower cell gate patterns and methods of forming the same
    33.
    发明申请
    SRAM cells having landing pad in contact with upper and lower cell gate patterns and methods of forming the same 有权
    具有与上下单元栅极图案接触的着陆焊盘的SRAM单元及其形成方法

    公开(公告)号：US20060097328A1

    公开(公告)日：2006-05-11

    申请号：US11268138

    申请日：2005-11-07

    申请人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

    发明人： Sung-Jin Kim ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Kun-Ho Kwak ,  Jong-Hyuk Kim ,  Jae-Joo Shim

    IPC分类号： H01L29/76

    CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903

    摘要： SRAM cells having landing pads in contact with upper and lower cell gate patterns, and methods of forming the same are provided. The SRAM cells and the methods remove the influence resulting from structural characteristics of the SRAM cells having vertically stacked upper and lower gate patterns, for stably connecting the patterns on the overall surface of the semiconductor substrate. An isolation layer isolating at least one lower active region is formed in a semiconductor substrate of the cell array region. The lower active region has two lower cell gate patterns. A body pattern is disposed in parallel with the semiconductor substrate. The body pattern is formed to confine an upper active region, which has upper cell gate patterns on the lower cell gate patterns. A landing pad is disposed between the lower cell gate patterns. A node pattern is formed to simultaneously contact the upper cell gate pattern and the lower cell gate pattern.

    摘要翻译： 提供了具有与上下单元栅极图案接触的接合焊盘的SRAM单元及其形成方法。 SRAM单元和该方法消除了具有垂直堆叠的上和下栅极图案的SRAM单元的结构特性所产生的影响，用于稳定地连接半导体衬底的整个表面上的图案。 在电池阵列区域的半导体衬底中形成隔离至少一个下部有源区的隔离层。 下部有源区域具有两个较低的单元栅极图案。 主体图案与半导体衬底平行设置。 形成主体图形以限制在下单元门图案上具有上单元栅极图案的上有源区。 着陆垫设置在下单元栅极图案之间。 形成节点图案以同时接触上单元格栅图案和下单元栅格图案。

    Mobile communication apparatus including antenna array and mobile communication method
    34.
    发明授权
    Mobile communication apparatus including antenna array and mobile communication method 有权
    包括天线阵列和移动通信方法的移动通信装置

    公开(公告)号：US07031664B2

    公开(公告)日：2006-04-18

    申请号：US10505559

    申请日：2003-02-17

    申请人： Yong-Suk Lee ,  Sung-Jin Kim ,  Kwang-Bok Lee ,  Keun-Chul Hwang

    发明人： Yong-Suk Lee ,  Sung-Jin Kim ,  Kwang-Bok Lee ,  Keun-Chul Hwang

    IPC分类号： H04B17/00

    CPC分类号： H04B7/0639 ,  H04B7/0617 ,  H04B7/0658

    摘要： Provided are a mobile communication apparatus including an antenna array and a mobile communication method. The mobile communication apparatus has a base station and a mobile station. The mobile station measures the downlink characteristics, detects physical space information and approximate long-term information, produces short-term informatio, transforms the short-term information and the physical space information into a feedback signal, and transmits the feedback signal to the base station. The base station receives the feedback signal, extracts weighted information, beamforms dedicated physical channel signals, combines pilot channel signals with the result of the beamforming, and transmits the results of the combinations to the mobile station via the antenna array. The physical space information denotes space information about the location of the mobile station with respect to the base station, and the approximate long-term information denotes long-term information. Accordingly, degradation of the performance of communications caused by a great amount of information to be fed back station can be prevented while keeping a beamforming gain.

    摘要翻译： 提供一种包括天线阵列和移动通信方法的移动通信装置。 移动通信装置具有基站和移动台。 移动台测量下行链路特性，检测物理空间信息和近似长期信息，产生短期信息，将短期信息和物理空间信息转换为反馈信号，并将反馈信号发送到基站 。 基站接收反馈信号，提取加权信息，波束形成专用物理信道信号，将导频信道信号与波束形成结果相结合，并通过天线阵列将结果结果发送给移动台。 物理空间信息表示关于移动台相对于基站的位置的空间信息，近似长期信息表示长期信息。 因此，可以在保持波束形成增益的同时防止由大量反馈站信息引起的通信性能的劣化。

    Apparatus and method for generating control signals to regulate gain levels of color signals
    37.
    发明申请
    Apparatus and method for generating control signals to regulate gain levels of color signals 审中-公开
    用于产生控制信号以调节彩色信号增益水平的装置和方法

    公开(公告)号：US20060012688A1

    公开(公告)日：2006-01-19

    申请号：US11168762

    申请日：2005-06-29

    申请人： Sung-Jin Kim

    发明人： Sung-Jin Kim

    IPC分类号： H04N9/73

    CPC分类号： H04N9/735

    摘要： An apparatus and method for generating control signals to regulate gain levels of color signals based on color data of which color gains are not regulated and color data of which color gains are regulated. The apparatus and method include generating first control signals to regulate the gain levels of the plurality of color signals based on a plurality of color signals of which gain levels are not regulated, calculating correction values to correct the first control signals based on a plurality of color signals of which gain levels are regulated, and generating second control signals which are results of correcting the first control signals by the correction values.

    摘要翻译： 一种用于产生控制信号的装置和方法，用于基于不调节颜色增益的颜色数据和调节颜色增益的颜色数据来调节彩色信号的增益水平。 该装置和方法包括：产生第一控制信号，以便根据增益电平不被调节的多个彩色信号来调节多个彩色信号的增益电平;计算校正值，以便基于多个颜色校正第一控制信号 增益电平被调节的信号，以及产生作为校正值的第一控制信号校正结果的第二控制信号。

    Method of fabricating an optical fiber preform and drawing of an optical fiber
    38.
    发明申请
    Method of fabricating an optical fiber preform and drawing of an optical fiber 审中-公开
    光纤预制棒的制造方法和光纤的拉制

    公开(公告)号：US20050223749A1

    公开(公告)日：2005-10-13

    申请号：US10942223

    申请日：2004-09-16

    申请人： Sung-Koog Oh ,  Sung-Jin Kim

    发明人： Sung-Koog Oh ,  Sung-Jin Kim

    IPC分类号： C03B37/00 ,  C03B37/012 ,  C03B37/027 ,  G02B6/00

    CPC分类号： C03B37/01245 ,  C03B37/02754 ,  Y02P40/57

    摘要： A method of fabricating an optical fiber preform using an overcladding device and an optical-fiber-drawing method are provided. The overcladding device includes first and second chucks, an annular oxygen-hydrogen burner, a furnace, and a carriage for reciprocating between the first and second chucks positioned on a shelf, and a vacuum pump coupled to one of the chucks. According to the preform-fabricating method, primary and secondary preforms fixed to the first and second chucks are leveled respectively. The primary preform is inserted coaxially into the secondary preform. The secondary preform is pre-heated using the furnace and heated using the oxygen-hydrogen burner, thus softening the preforms. A first end of the secondary preform is sealed by heating the first end using the furnace, and the primary and secondary preforms are collapsed by forming a negative-pressure vacuum state inside the secondary preform through a second end of the secondary preform.

    摘要翻译： 提供了使用外包装置制造光纤预制件的方法和光纤拉伸方法。 外包装装置包括第一和第二卡盘，环形氧氢燃烧器，炉子和用于在定位在搁架上的第一和第二卡盘之间往复运动的托架，以及联接到卡盘之一的真空泵。 根据预制件制造方法，固定在第一和第二卡盘上的一次和二次预成型件分别平整。 初级预制件同轴地插入次级预制件中。 使用炉子对二次预制件进行预热，并使用氧 - 氢燃烧器加热，从而软化预制件。 通过使用炉加热第一端来密封二次预制件的第一端，并且通过在次级预制件的第二端在第二预制件内部形成负压真空状态来使第一和第二预成型件折叠。

    Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques and semiconductor integrated circuits fabricated thereby
    39.
    发明申请
    Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques and semiconductor integrated circuits fabricated thereby 失效
    使用选择性外延生长和部分平面化技术制造半导体集成电路的方法和由此制造的半导体集成电路

    公开(公告)号：US20050184292A1

    公开(公告)日：2005-08-25

    申请号：US11065750

    申请日：2005-02-24

    申请人： Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

    发明人： Kun-Ho Kwak ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Won-Seok Cho ,  Hoon Lim ,  Sung-Jin Kim ,  Byung-Jun Hwang ,  Jong-Hyuk Kim

    IPC分类号： H01L21/8244 ,  H01L27/108 ,  H01L27/11

    CPC分类号： H01L27/1108 ,  H01L27/11

    摘要： Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

    摘要翻译： 提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。 所述方法包括在单晶半导体衬底上形成层间绝缘层。 单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。 单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。 结果，半导体本体包括单晶外延半导体图案的至少一部分。 因此，半导体本体具有优异的单晶结构。 还提供了使用这些方法制造的半导体集成电路。