公开(公告)号：US07880503B2

公开(公告)日：2011-02-01

申请号：US12503145

申请日：2009-07-15

Applicant: Yeong-Keun Kwon ,  Sang-Jin Jeon ,  Yoon-Jang Kim ,  Bae-Heuk Yim ,  Bon-Yong Koo

Inventor： Yeong-Keun Kwon ,  Sang-Jin Jeon ,  Yoon-Jang Kim ,  Bae-Heuk Yim ,  Bon-Yong Koo

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: G11C8/08 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184

Abstract: A method of driving gate lines is used to activate the gate lines by outputting output signals of stages to the gate lines. A first node is boosted up based upon a carry signal or the vertical start signal from a previous stage. A gate signal that is pulled up is outputted through an output terminal of a present stage based upon a first clock signal which is boosted up. An off-voltage is outputted through the output terminal of the present stage in response to an output signal from a next stage or the vertical start signal. The first node is discharged in response to the output signal from the next stage or a carry signal from a last stage. A positive ripple voltage at the first node is removed by providing a negative ripple voltage to the first node.

Abstract translation: 驱动栅极线的方法用于通过将栅极线的输出信号输出来激活栅极线。 基于进位信号或来自前一级的垂直起始信号来升高第一节点。 基于提升的第一时钟信号，通过当前级的输出端输出被上拉的门信号。 响应于来自下一级的输出信号或垂直起始信号，通过当前级的输出端输出截止电压。 第一节点响应于来自下一级的输出信号或来自最后一级的进位信号而放电。 通过向第一节点提供负纹波电压来消除第一节点处的正纹波电压。

公开(公告)号：US20100207667A1

公开(公告)日：2010-08-19

申请号：US12503145

申请日：2009-07-15

Applicant: Yeong-Keun Kwon ,  Sang-Jin Jeon ,  Yoon-Jang Kim ,  Bae-Heuk Yim ,  Bon-Yong Koo

Inventor： Yeong-Keun Kwon ,  Sang-Jin Jeon ,  Yoon-Jang Kim ,  Bae-Heuk Yim ,  Bon-Yong Koo

IPC: H03B1/00 ,  G09G5/00

CPC classification number: G11C8/08 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184

Abstract: A method of driving gate lines is used to activate the gate lines by outputting output signals of stages to the gate lines. A first node is boosted up based upon a carry signal or the vertical start signal from a previous stage. A gate signal that is pulled up is outputted through an output terminal of a present stage based upon a first clock signal which is boosted up. An off-voltage is outputted through the output terminal of the present stage in response to an output signal from a next stage or the vertical start signal. The first node is discharged in response to the output signal from the next stage or a carry signal from a last stage. A positive ripple voltage at the first node is removed by providing a negative ripple voltage to the first node.

Abstract translation: 驱动栅极线的方法用于通过将栅极线的输出信号输出来激活栅极线。 基于进位信号或来自前一级的垂直起始信号来升高第一节点。 基于提升的第一时钟信号，通过当前级的输出端输出被上拉的门信号。 响应于来自下一级的输出信号或垂直起动信号，通过本级的输出端输出截止电压。 第一节点响应于来自下一级的输出信号或来自最后一级的进位信号而放电。 通过向第一节点提供负纹波电压来消除第一节点处的正纹波电压。

公开(公告)号：US07504848B2

公开(公告)日：2009-03-17

申请号：US11857889

申请日：2007-09-19

Applicant: Sang-Jin Jeon

Inventor： Sang-Jin Jeon

IPC: G01R31/00

CPC classification number: G09G3/006

Abstract: A panel for a display device includes a display area and a peripheral area. The display area comprises a plurality of pixels each comprising a switching element and gate lines and data lines connected to the pixels. The peripheral area comprises a plurality of gate driving integrated circuit regions, a plurality of data driving integrated circuit regions, a plurality of repair lines disposed along the edge of the panel, connecting pads connected to both ends of the repair lines, a test line connected to at least one connecting pad, and a test pad connected to the test line. A test method for detecting disconnection of the data lines is also provided.

Abstract translation: 用于显示装置的面板包括显示区域和外围区域。 显示区域包括多个像素，每个像素包括开关元件和连接到像素的栅极线和数据线。 外围区域包括多个栅极驱动集成电路区域，多个数据驱动集成电路区域，沿着面板边缘设置的多个修复线，连接到修复线两端的连接焊盘，连接的测试线 至少一个连接焊盘和连接到测试线的测试焊盘。 还提供了用于检测数据线断开的测试方法。

公开(公告)号：US07459323B2

公开(公告)日：2008-12-02

申请号：US11512805

申请日：2006-08-30

Applicant: Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

Inventor： Min-Wook Park ,  Sang-Jin Jeon ,  Jung-Joon Park ,  Jeong-Young Lee ,  Bum-Ki Baek ,  Se-Hwan Yu ,  Sang-Ki Kwak ,  Han-Ju Lee ,  Kwon-Young Choi

IPC: H01L21/00

CPC classification number: G02F1/1368 ,  G02F1/1339

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Abstract translation: 提供一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜，下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极，所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。

公开(公告)号：US20080273003A1

公开(公告)日：2008-11-06

申请号：US12079559

申请日：2008-03-26

Applicant: Sang-Jin Jeon

Inventor： Sang-Jin Jeon

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G02F1/1345 ,  G09G3/3666 ,  G09G2300/0426

Abstract: An LCD device includes first and second gate drivers coupled on a side of an LCD panel displaying an image, a data driver coupled to the LCD panel adjacent to the second gate driver, a timing controller generating a gate start pulse applied to the first gate driver and control signals applied to the data driver, and at least one gate start pulse supply line supplying the gate start pulse to the first gate driver, a manufacturing method thereof and a driving method thereof.

Abstract translation: LCD装置包括耦合在显示图像的LCD面板一侧的第一和第二栅极驱动器，耦合到与第二栅极驱动器相邻的LCD面板的数据驱动器，定时控制器，产生施加到第一栅极驱动器的栅极起始脉冲 以及施加到数据驱动器的控制信号，以及向第一栅极驱动器提供栅极起始脉冲的至少一个栅极起始脉冲供给线，其制造方法及其驱动方法。

公开(公告)号：US20080007287A1

公开(公告)日：2008-01-10

申请号：US11857889

申请日：2007-09-19

Applicant: Sang-Jin Jeon

Inventor： Sang-Jin Jeon

IPC: G01R31/00

CPC classification number: G09G3/006

Abstract: A panel for a display device includes a display area and a peripheral area. The display area comprises a plurality of pixels each comprising a switching element and gate lines and data lines connected to the pixels. The peripheral area comprises a plurality of gate driving integrated circuit regions, a plurality of data driving integrated circuit regions, a plurality of repair lines disposed along the edge of the panel, connecting pads connected to both ends of the repair lines, a test line connected to at least one connecting pad, and a test pad connected to the test line. A test method for detecting disconnection of the data lines is also provided.

Abstract translation: 用于显示装置的面板包括显示区域和外围区域。 显示区域包括多个像素，每个像素包括开关元件和连接到像素的栅极线和数据线。 外围区域包括多个栅极驱动集成电路区域，多个数据驱动集成电路区域，沿着面板边缘设置的多个修复线，连接到修复线两端的连接焊盘，连接的测试线 至少一个连接焊盘和连接到测试线的测试焊盘。 还提供了用于检测数据线断开的测试方法。

公开(公告)号：US09079992B2

公开(公告)日：2015-07-14

申请号：US13980860

申请日：2012-01-19

Applicant: Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An ,  Sang-Jin Jeon ,  Cheon-Il Park ,  Choong-Hoon Lee

Inventor： Kyung-Seop Noh ,  Nan-Young Lee ,  Won-Hee Kim ,  Sang-Eun An ,  Sang-Jin Jeon ,  Cheon-Il Park ,  Choong-Hoon Lee

IPC: C08F210/16 ,  C08F4/6592 ,  C08F4/653 ,  C08L23/08 ,  C08L23/14 ,  C08F297/08

CPC classification number: C08F295/00 ,  C08F4/64013 ,  C08F4/65904 ,  C08F4/6592 ,  C08F210/16 ,  C08F297/08 ,  C08L23/08 ,  C08L23/0815 ,  C08L23/14 ,  C08L23/142 ,  C08F4/64044 ,  C08F210/00

Abstract: The present description relates to an olefin block copolymer having excellences in elasticity and heat resistance and its preparation method. The olefin block copolymer includes a plurality of blocks or segments, each of which includes an ethylene or propylene repeating unit and an α-olefin repeating unit at different weight fractions. The olefin block copolymer has a density of 0.85 to 0.92 g/cm3, and density X (g/cm3) and TMA (Thermal Mechanical Analysis) value Y (° C.) satisfy a defined relationship.

Abstract translation: 本发明涉及具有优异的弹性和耐热性的烯烃嵌段共聚物及其制备方法。 烯烃嵌段共聚物包括多个嵌段或链段，其各自包括不同重量分数的乙烯或丙烯重复单元和α-烯烃重复单元。 烯烃嵌段共聚物的密度为0.85〜0.92g / cm 3，密度X（g / cm 3）和TMA（热机械分析）值Y（℃）满足规定的关系。

公开(公告)号：US09062146B2

公开(公告)日：2015-06-23

申请号：US13980870

申请日：2012-01-20

Applicant: Kyung-Seop Noh ,  Won-Hee Kim ,  Nan-Young Lee ,  Sang-Jin Jeon ,  Sang-Eun An

Inventor： Kyung-Seop Noh ,  Won-Hee Kim ,  Nan-Young Lee ,  Sang-Jin Jeon ,  Sang-Eun An

IPC: C08F210/16 ,  C08F297/08 ,  C08F301/00 ,  C08F4/659 ,  C08F4/6592

CPC classification number: C08F297/083 ,  C08F4/65908 ,  C08F4/6592 ,  C08F210/16 ,  C08F301/00 ,  C08F2410/01 ,  C08F2500/10 ,  C08F4/65904 ,  C08F4/64044 ,  C08F210/14 ,  C08F2500/12 ,  C08F2500/08 ,  C08F2500/03

Abstract: The present description relates to an olefin block copolymer having excellences in elasticity, heat resistance, and processability. The olefin block copolymer includes a plurality of blocks or segments, each of which includes an ethylene or propylene repeating unit and an α-olefin repeating unit at different weight fractions. In the olefin block copolymer, a first derivative of the number Y of short-chain branches (SCBs) per 1,000 carbon atoms of each polymer chain contained in the block copolymer with respect to the molecular weight X of the polymer chains is a negative or positive number of −1.5×10−4 or greater; and the first derivative is from −1.0×10−4 to 1.0×10−4 in the region corresponding to the median of the molecular weight X or above.

Abstract translation: 本发明涉及具有优异的弹性，耐热性和加工性的烯烃嵌段共聚物。 烯烃嵌段共聚物包括多个嵌段或链段，其各自包括不同重量分数的乙烯或丙烯重复单元和α-烯烃重复单元。 在烯烃嵌段共聚物中，相对于聚合物链的分子量X，包含在嵌段共聚物中的每个聚合物链的每1000个碳原子的短链分支数（SCB）的第一个Y的一级导数是负的或正的 数量为-1.5×10-4以上; 在对应于分子量X或更高的中位数的区域中，第一衍生物为-1.0×10-4至1.0×10-4。

公开(公告)号：US08735312B2

公开(公告)日：2014-05-27

申请号：US13642203

申请日：2011-04-25

Applicant: Kyung-Seop Noh ,  Hoon Chae ,  Cheon-Il Park ,  Won-Hee Kim ,  Sang-Jin Jeon ,  Eun-Jung Lee ,  Choong-Hoon Lee ,  Jong-Joo Ha

Inventor： Kyung-Seop Noh ,  Hoon Chae ,  Cheon-Il Park ,  Won-Hee Kim ,  Sang-Jin Jeon ,  Eun-Jung Lee ,  Choong-Hoon Lee ,  Jong-Joo Ha

IPC: C08F4/653 ,  C08F4/6592 ,  C08F10/00

CPC classification number: C08F4/76 ,  C08F4/65908 ,  C08F4/6592 ,  C08F210/14 ,  C08F210/16 ,  C08F2410/01 ,  C08F2420/02 ,  C08F2500/12 ,  C08F2500/08 ,  C08F10/00 ,  C08F4/64044 ,  C08F4/64048 ,  C08F4/65904

Abstract: The present invention relates to a catalyst composition and a process for preparing an olefin polymer using the same. More specifically, the present invention relates to a novel catalyst composition comprising at least two types of catalysts and a process for preparing an olefin polymer having excellent heat resistance using the same. The present invention can provide an olefin polymer having excellent activity and high heat resistance, and also can control the values of density, heat resistance and melt index (MI) of the olefin polymer.

Abstract translation: 本发明涉及催化剂组合物和使用其制备烯烃聚合物的方法。 更具体地，本发明涉及包含至少两种类型的催化剂的新型催化剂组合物和使用其制备具有优异耐热性的烯烃聚合物的方法。 本发明可以提供具有优异活性和高耐热性的烯烃聚合物，并且还可以控制烯烃聚合物的密度，耐热性和熔体指数（MI）的值。

公开(公告)号：US07580088B2

公开(公告)日：2009-08-25

申请号：US11854059

申请日：2007-09-12

Applicant: Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

Inventor： Jang-Soo Kim ,  Hyang-Shik Kong ,  Min-Wook Park ,  Sang-Jin Jeon

IPC: G02F1/136 ,  H01L21/4763

CPC classification number: G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1288 ,  H01L29/66765

Abstract: A device and corresponding method of fabrication thereof are disclosed, where the device provides a contact for semiconductor and display devices, the device including a substrate, a first wiring line assembly formed on the substrate, an under-layer formed on the first wiring line assembly, an organic insulating layer formed on the under-layer such that the organic insulating layer covers the under-layer, a pattern on the organic insulating layer for contact holes to expose the under-layer, etched contact holes formed in the under-layer in correspondence with the pattern such that the underlying first wiring line assembly is exposed to the outside, a cured organic insulating layer formed on the under-layer, and a second wiring line assembly formed on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the etched contact holes, and the corresponding method of fabrication including forming a first wiring line assembly on a substrate, forming an under-layer on the first wiring line assembly, forming an organic insulating layer such that the organic insulating layer covers the under-layer patterning the organic insulating layer to thereby form contact holes exposing the under-layer, etching the under-layer exposed through the contact holes such that the underlying first wiring line assembly is exposed to the outside, curing the organic insulating layer, and forming a second wiring line assembly on the organic insulating layer such that the second wiring line assembly is connected to the first wiring line assembly through the contact holes.

Abstract translation: 公开了一种器件及其相应的制造方法，其中器件为半导体和显示器件提供接触，该器件包括衬底，形成在衬底上的第一布线组件，形成在第一布线组件上的底层 形成在下层上的有机绝缘层，使得有机绝缘层覆盖下层，在有机绝缘层上形成用于接触孔的图案，以暴露下层中形成的下层的蚀刻接触孔， 与图案对应，使得下面的第一布线组件暴露于外部，形成在下层上的固化的有机绝缘层和形成在有机绝缘层上的第二布线组件，使得第二布线组件是 通过蚀刻的接触孔连接到第一布线组件，以及相应的制造方法，包括形成第一布线组件 在第一布线组件上形成底层，形成有机绝缘层，使得有机绝缘层覆盖图案化有机绝缘层的下层，从而形成暴露下层，蚀刻的接触孔 所述下层通过所述接触孔暴露，使得所述下面的第一布线组件暴露于外部，固化所述有机绝缘层，以及在所述有机绝缘层上形成第二布线组合件，使得所述第二布线组件被连接 通过接触孔到第一布线组件。