公开(公告)号：US07880503B2

公开(公告)日：2011-02-01

申请号：US12503145

申请日：2009-07-15

申请人： Yeong-Keun Kwon ,  Sang-Jin Jeon ,  Yoon-Jang Kim ,  Bae-Heuk Yim ,  Bon-Yong Koo

发明人： Yeong-Keun Kwon ,  Sang-Jin Jeon ,  Yoon-Jang Kim ,  Bae-Heuk Yim ,  Bon-Yong Koo

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： G11C8/08 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184

摘要： A method of driving gate lines is used to activate the gate lines by outputting output signals of stages to the gate lines. A first node is boosted up based upon a carry signal or the vertical start signal from a previous stage. A gate signal that is pulled up is outputted through an output terminal of a present stage based upon a first clock signal which is boosted up. An off-voltage is outputted through the output terminal of the present stage in response to an output signal from a next stage or the vertical start signal. The first node is discharged in response to the output signal from the next stage or a carry signal from a last stage. A positive ripple voltage at the first node is removed by providing a negative ripple voltage to the first node.

摘要翻译： 驱动栅极线的方法用于通过将栅极线的输出信号输出来激活栅极线。 基于进位信号或来自前一级的垂直起始信号来升高第一节点。 基于提升的第一时钟信号，通过当前级的输出端输出被上拉的门信号。 响应于来自下一级的输出信号或垂直起始信号，通过当前级的输出端输出截止电压。 第一节点响应于来自下一级的输出信号或来自最后一级的进位信号而放电。 通过向第一节点提供负纹波电压来消除第一节点处的正纹波电压。

公开(公告)号：US20100207667A1

公开(公告)日：2010-08-19

申请号：US12503145

申请日：2009-07-15

申请人： Yeong-Keun Kwon ,  Sang-Jin Jeon ,  Yoon-Jang Kim ,  Bae-Heuk Yim ,  Bon-Yong Koo

发明人： Yeong-Keun Kwon ,  Sang-Jin Jeon ,  Yoon-Jang Kim ,  Bae-Heuk Yim ,  Bon-Yong Koo

IPC分类号： H03B1/00 ,  G09G5/00

CPC分类号： G11C8/08 ,  G09G3/3674 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184

摘要： A method of driving gate lines is used to activate the gate lines by outputting output signals of stages to the gate lines. A first node is boosted up based upon a carry signal or the vertical start signal from a previous stage. A gate signal that is pulled up is outputted through an output terminal of a present stage based upon a first clock signal which is boosted up. An off-voltage is outputted through the output terminal of the present stage in response to an output signal from a next stage or the vertical start signal. The first node is discharged in response to the output signal from the next stage or a carry signal from a last stage. A positive ripple voltage at the first node is removed by providing a negative ripple voltage to the first node.

摘要翻译： 驱动栅极线的方法用于通过将栅极线的输出信号输出来激活栅极线。 基于进位信号或来自前一级的垂直起始信号来升高第一节点。 基于提升的第一时钟信号，通过当前级的输出端输出被上拉的门信号。 响应于来自下一级的输出信号或垂直起动信号，通过本级的输出端输出截止电压。 第一节点响应于来自下一级的输出信号或来自最后一级的进位信号而放电。 通过向第一节点提供负纹波电压来消除第一节点处的正纹波电压。

公开(公告)号：US08232984B2

公开(公告)日：2012-07-31

申请号：US12559893

申请日：2009-09-15

申请人： Yeong-Keun Kwon ,  Yun-Hee Kwak ,  Bae-Heuk Yim ,  Jeong-Il Kim ,  Bon-Yong Koo ,  Mi-Sun Lee

发明人： Yeong-Keun Kwon ,  Yun-Hee Kwak ,  Bae-Heuk Yim ,  Jeong-Il Kim ,  Bon-Yong Koo ,  Mi-Sun Lee

IPC分类号： G06F3/038

CPC分类号： G09G3/006 ,  G09G3/3677 ,  G09G2310/0267 ,  G11C19/184

摘要： The present invention relates to a thin film transistor array panel and a display device including the same. A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a plurality of gate lines; a plurality of pixels respectively connected to the gate lines; a gate driver comprising a plurality of stages connected to each other, the plurality of stages being respectively connected to the plurality of gate lines and applying gate signals to the plurality of gate lines; and a driver inspection unit separated from the gate driver and including at least three inspection stages, wherein each of the at least three inspection stages has a same structure as one of the plurality of stages of the gate driver.

摘要翻译： 薄膜晶体管阵列面板及其显示装置技术领域本发明涉及薄膜晶体管阵列面板及其构成。 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：多条栅极线; 分别连接到所述栅极线的多个像素; 栅极驱动器，其包括彼此连接的多个级，所述多个级分别连接到所述多条栅极线并将栅极信号施加到所述多条栅极线; 以及驱动器检查单元，其与所述门驱动器分离并且包括至少三个检查级，其中所述至少三个检查级中的每一个具有与所述多个级驱动器中的一级相同的结构。

公开(公告)号：US08101445B2

公开(公告)日：2012-01-24

申请号：US12496101

申请日：2009-07-01

申请人： Bon-Yong Koo ,  Bae-Heuk Yim

发明人： Bon-Yong Koo ,  Bae-Heuk Yim

IPC分类号： H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/124

摘要： A thin film transistor array panel according to the present invention includes: an insulation substrate having a display area and a peripheral area; a plurality of thin film transistors disposed in the display area; a plurality of gate lines connected to the thin film transistors; a plurality of data lines connected to the thin film transistors; a driving unit disposed in the peripheral area of the insulation substrate, and controlling the thin film transistor; a plurality of signal lines connecting between the driving unit and the gate lines or the data lines; and a dummy pattern overlapping the signal line and made of a transparent conductive material.

摘要翻译： 根据本发明的薄膜晶体管阵列板包括：具有显示区域和周边区域的绝缘基板; 设置在所述显示区域中的多个薄膜晶体管; 连接到所述薄膜晶体管的多个栅极线; 连接到所述薄膜晶体管的多条数据线; 驱动单元，设置在所述绝缘基板的周边区域中，并控制所述薄膜晶体管; 连接在驱动单元和栅极线或数据线之间的多条信号线; 以及与信号线重叠并由透明导电材料制成的虚拟图案。

公开(公告)号：US20100187538A1

公开(公告)日：2010-07-29

申请号：US12496101

申请日：2009-07-01

申请人： Bon-Yong Koo ,  Bae-Heuk Yim

发明人： Bon-Yong Koo ,  Bae-Heuk Yim

IPC分类号： H01L33/00 ,  H01L21/28

CPC分类号： H01L27/1288 ,  H01L27/124

摘要： A thin film transistor array panel according to the present invention includes: an insulation substrate having a display area and a peripheral area; a plurality of thin film transistors disposed in the display area; a plurality of gate lines connected to the thin film transistors; a plurality of data lines connected to the thin film transistors; a driving unit disposed in the peripheral area of the insulation substrate, and controlling the thin film transistor; a plurality of signal lines connecting between the driving unit and the gate lines or the data lines; and a dummy pattern overlapping the signal line and made of a transparent conductive material.

摘要翻译： 根据本发明的薄膜晶体管阵列板包括：具有显示区域和周边区域的绝缘基板; 设置在所述显示区域中的多个薄膜晶体管; 连接到所述薄膜晶体管的多个栅极线; 连接到所述薄膜晶体管的多条数据线; 驱动单元，设置在所述绝缘基板的周边区域中，并控制所述薄膜晶体管; 连接在驱动单元和栅极线或数据线之间的多条信号线; 以及与信号线重叠并由透明导电材料制成的虚拟图案。

公开(公告)号：US07898635B2

公开(公告)日：2011-03-01

申请号：US11871526

申请日：2007-10-12

申请人： Bae-Heuk Yim ,  Jeong-Ho Lee ,  Doo-Hwan You ,  Seong-Young Lee

发明人： Bae-Heuk Yim ,  Jeong-Ho Lee ,  Doo-Hwan You ,  Seong-Young Lee

IPC分类号： G02F1/1339

CPC分类号： G02F1/13394 ,  G02F1/1339 ,  G02F1/1345 ,  G02F1/1362

摘要： A liquid crystal display includes a conductive spacer that connects a common voltage line of an array substrate to a common electrode of an opposite substrate. The conductive spacer has a bar-like shape and extends along the common voltage line.

摘要翻译： 液晶显示器包括将阵列基板的公共电压线连接到相对基板的公共电极的导电间隔件。 导电间隔物具有棒状形状并且沿着公共电压线延伸。

公开(公告)号：US07902006B2

公开(公告)日：2011-03-08

申请号：US12436356

申请日：2009-05-06

申请人： Woong-Kwon Kim ,  Ho-Jun Lee ,  Hong-Kee Chin ,  Sang-Heon Song ,  Jung-Suk Bang ,  Jun-Ho Song ,  Byeong-Jae Ahn ,  Bae-Heuk Yim

发明人： Woong-Kwon Kim ,  Ho-Jun Lee ,  Hong-Kee Chin ,  Sang-Heon Song ,  Jung-Suk Bang ,  Jun-Ho Song ,  Byeong-Jae Ahn ,  Bae-Heuk Yim

IPC分类号： H01L21/00 ,  H01L21/84 ,  G02F1/1343 ,  G02F1/1333

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1255

摘要： In manufacturing a thin film transistor array substrate, a passivation film is formed over the transistors. A first photoresist pattern is formed over the passivation film, with a first portion partially overlying at least one source/drain electrode of each transistor and overlying each pixel electrode region, and with a second portion thicker than the first portion. The passivation film is patterned using the first photoresist pattern as a mask. The first photoresist pattern's first portion is removed to form a second photoresist pattern which protrudes upward around the pixel electrode regions. A transparent conductive film is formed with recesses in the pixel electrode regions. A masking pattern is formed over the transparent film in each pixel electrode region, the masking pattern's top surface being below a top of the transparent film. The transparent film is patterned using the masking pattern as a mask to form the pixel electrodes.

摘要翻译： 在制造薄膜晶体管阵列基板时，在晶体管上形成钝化膜。 在钝化膜上形成第一光致抗蚀剂图案，其中第一部分部分地覆盖每个晶体管的至少一个源极/漏电极并且覆盖每个像素电极区域，并且具有比第一部分更厚的第二部分。 使用第一光致抗蚀剂图案作为掩模来图案化钝化膜。 去除第一光致抗蚀剂图案的第一部分以形成在像素电极区域周围向上突出的第二光致抗蚀剂图案。 透明导电膜在像素电极区域中形成有凹陷。 在每个像素电极区域中的透明膜上形成掩模图案，掩模图案的顶表面在透明膜的顶部之下。 使用掩模图案作为掩模来对透明膜进行图案化以形成像素电极。

公开(公告)号：US07920243B2

公开(公告)日：2011-04-05

申请号：US11181135

申请日：2005-07-13

申请人： Jeong-Ho Lee ,  Kye-Hun Lee ,  Kweon-Sam Hong ,  Bae-Heuk Yim

发明人： Jeong-Ho Lee ,  Kye-Hun Lee ,  Kweon-Sam Hong ,  Bae-Heuk Yim

IPC分类号： G02F1/1335 ,  G02F1/1339

CPC分类号： G02F1/133514 ,  G02F1/13394

摘要： A color filter substrate includes a transparent substrate, a light-blocking layer, a color filter layer, a first cell gap maintaining member and a second cell gap maintaining member. The transparent substrate has a plurality of pixel regions. Each of the pixel regions includes first and second regions. The light-blocking layer is disposed over the transparent substrate. The light-blocking layer blocks light that leaks through boundaries of the pixel regions. The color filter layer is disposed over the transparent substrate. The color filter layer has a first thickness at the first region and a second thickness that is smaller than the first thickness at the second region. The first cell gap maintaining member is disposed at the first region. The second cell gap maintaining member is disposed at the second region. Therefore, a height difference between the main column spacer and the sub column spacer may be easily adjusted.

摘要翻译： 滤色器基板包括透明基板，遮光层，滤色器层，第一单元间隙保持部件和第二单元间隙保持部件。 透明基板具有多个像素区域。 每个像素区域包括第一和第二区域。 遮光层设置在透明基板上。 遮光层阻挡通过像素区域的边界泄漏的光。 滤色器层设置在透明基板上。 滤色器层在第一区域具有第一厚度，在第二区域具有小于第一厚度的第二厚度。 第一细胞间隙保持部件设置在第一区域。 第二单元间隙保持构件设置在第二区域。 因此，可以容易地调整主柱间隔件和子柱间隔件之间的高度差。

公开(公告)号：US07916244B2

公开(公告)日：2011-03-29

申请号：US12389098

申请日：2009-02-19

申请人： Seung-Hyun Hur ,  Kweon-Sam Hong ,  Woo-Sung Sohn ,  Bae-Heuk Yim ,  Hyun-Ho Kang ,  Jae-Yong Shin

发明人： Seung-Hyun Hur ,  Kweon-Sam Hong ,  Woo-Sung Sohn ,  Bae-Heuk Yim ,  Hyun-Ho Kang ,  Jae-Yong Shin

IPC分类号： G02F1/1335

CPC分类号： G02F1/133707 ,  G02F1/13624 ,  G02F2001/134345 ,  G02F2201/122 ,  G02F2201/52 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/0452

摘要： A liquid crystal display (LCD) having high luminance and color renditions is provided. The liquid crystal display includes a first insulating substrate, a gate line and a data line crossing each other on the first insulating substrate to define a pixel. First and second sub-pixel electrodes divide the pixel into two parts. A first switching element drives the first sub-pixel electrode and a second switching element drives the second sub-pixel electrode. A second insulating substrate faces the first insulating substrate. A color pattern is arranged on the second insulating substrate and overlaps the first sub-pixel electrode. A contrast pattern overlaps the second sub-pixel electrode.

摘要翻译： 提供具有高亮度和彩色再现性的液晶显示器（LCD）。 液晶显示器包括在第一绝缘基板上彼此交叉的第一绝缘基板，栅极线和数据线，以限定像素。 第一和第二子像素电极将像素分成两部分。 第一开关元件驱动第一子像素电极，第二开关元件驱动第二子像素电极。 第二绝缘基板面向第一绝缘基板。 在第二绝缘基板上布置有彩色图案，并与第一子像素电极重叠。 对比度图案与第二子像素电极重叠。

公开(公告)号：US20100159652A1

公开(公告)日：2010-06-24

申请号：US12436356

申请日：2009-05-06

申请人： Woong-Kwon Kim ,  Ho-Jun Lee ,  Hong-Kee Chin ,  Sang-Heon Song ,  Jung-Suk Bank ,  Jun-Ho Song ,  Byeong-Jae Ahn ,  Bae-Heuk Yim

发明人： Woong-Kwon Kim ,  Ho-Jun Lee ,  Hong-Kee Chin ,  Sang-Heon Song ,  Jung-Suk Bank ,  Jun-Ho Song ,  Byeong-Jae Ahn ,  Bae-Heuk Yim

IPC分类号： H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1255

摘要： In manufacturing a thin film transistor array substrate, a passivation film is formed over the transistors. A first photoresist pattern is formed over the passivation film, with a first portion partially overlying at least one source/drain electrode of each transistor and overlying each pixel electrode region, and with a second portion thicker than the first portion. The passivation film is patterned using the first photoresist pattern as a mask. The first photoresist pattern's first portion is removed to form a second photoresist pattern which protrudes upward around the pixel electrode regions. A transparent conductive film is formed with recesses in the pixel electrode regions. A masking pattern is formed over the transparent film in each pixel electrode region, the masking pattern's top surface being below a top of the transparent film. The transparent film is patterned using the masking pattern as a mask to form the pixel electrodes.

摘要翻译： 在制造薄膜晶体管阵列基板时，在晶体管上形成钝化膜。 在钝化膜上形成第一光致抗蚀剂图案，其中第一部分部分地覆盖每个晶体管的至少一个源极/漏电极并且覆盖每个像素电极区域，并且具有比第一部分更厚的第二部分。 使用第一光致抗蚀剂图案作为掩模来图案化钝化膜。 去除第一光致抗蚀剂图案的第一部分以形成在像素电极区域周围向上突出的第二光致抗蚀剂图案。 透明导电膜在像素电极区域中形成有凹陷。 在每个像素电极区域中的透明膜上形成掩模图案，掩模图案的顶表面在透明膜的顶部之下。 使用掩模图案作为掩模来对透明膜进行图案化以形成像素电极。