公开(公告)号：US08097913B2

公开(公告)日：2012-01-17

申请号：US11891605

申请日：2007-08-10

申请人： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： An electrically erasable and programmable read only memory (EEPROM) device and a method of manufacturing the EEPROM device are provided. First and second gate structures having the same structure are formed on a tunnel insulating layer formed on a substrate, such that the first and second gate structures are spaced apart from each other. A common source region is formed at a portion of the substrate located between the first and second gate structures. First and second drain regions are formed at first and second portions of the substrate adjacent to the first and second gate structures, respectively. Thus, the EEPROM device is manufactured including first and second transistors that have the same structure and may alternately serve as a memory transistor and a selection transistor according to an applied signal.

摘要翻译： 提供电可擦除可编程只读存储器（EEPROM）器件和制造EEPROM器件的方法。 在形成在基板上的隧道绝缘层上形成具有相同结构的第一和第二栅极结构，使得第一和第二栅极结构彼此间隔开。 在位于第一和第二栅极结构之间的衬底的一部分处形成公共源区。 第一和第二漏极区分别形成在与第一和第二栅极结构相邻的衬底的第一和第二部分处。 因此，制造EEPROM器件，其包括具有相同结构的第一和第二晶体管，并且可以根据施加的信号交替地用作存储晶体管和选择晶体管。

公开(公告)号：US07936003B2

公开(公告)日：2011-05-03

申请号：US11344560

申请日：2006-01-31

申请人： Sang-Woo Kang ,  Jeong-Uk Han ,  Yong-Tae Kim ,  Seung-Beom Yoon

发明人： Sang-Woo Kang ,  Jeong-Uk Han ,  Yong-Tae Kim ,  Seung-Beom Yoon

IPC分类号： H01L29/788

CPC分类号： H01L29/785 ,  H01L27/105 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2436 ,  H01L29/7881 ,  H01L29/792

摘要： A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.

摘要翻译： 半导体器件包括具有垂直栅电极的晶体管。 在晶体管结构中，半导体图案具有面向横向的第一和第二侧以及纵向方向上的第三和第四侧。 栅极图案被布置成与半导体图案的第一和第二侧相邻。 杂质图案直接接触半导体图案的第三面和第四面。 栅极绝缘图案插入在栅极图案和半导体图案之间。

公开(公告)号：US20080128783A1

公开(公告)日：2008-06-05

申请号：US12027771

申请日：2008-02-07

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

摘要： A split-gate non-volatile memory device includes a raised oxide layer on a field oxide region between adjacent split-gate memory cells, the raised oxide layer extending onto first and second floating gates included in the adjacent split-gate memory cells covered by a wordline electrically coupled to respective control gates included in the adjacent split-gate memory cells.

摘要翻译： 分闸非易失性存储器件包括在相邻的分裂栅极存储器单元之间的场氧化物区域上的凸起的氧化物层，所述凸起的氧化物层延伸到包括在相邻的分离栅极存储器单元中的第一和第二浮动栅极上， 字线电耦合到相邻分离门存储器单元中包括的相应控制门。

公开(公告)号：US20060170028A1

公开(公告)日：2006-08-03

申请号：US11323355

申请日：2005-12-30

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

摘要： A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

摘要翻译： 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

公开(公告)号：US08604535B2

公开(公告)日：2013-12-10

申请号：US12648386

申请日：2009-12-29

申请人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788 ,  H01L21/762

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory device includes an active region in which a channel of a transistor is formed in a substrate, element isolation films defining the active region and formed on the substrate at both sides of the channel at a height lower than an upper surface of the active region, a first dielectric layer, a second dielectric layer, and a control gate electrode formed on the active region in this order, and a floating gate electrode formed between the first dielectric layer and the second dielectric layer so as to intersect the length direction of the channel and extend to the upper surfaces of the element isolation films at both sides of the channel, thereby surrounding the channel.

摘要翻译： 非易失性存储器件包括其中在衬底中形成晶体管的沟道的有源区，限定有源区的元件隔离膜，并且形成在通道两侧的基底上，高度低于 有源区，第一电介质层，第二电介质层和控制栅电极，以及在第一介电层和第二电介质层之间形成的与栅极的长度相交的浮栅， 通道的方向并延伸到通道两侧的元件隔离膜的上表面，从而围绕通道。

公开(公告)号：US08059473B2

公开(公告)日：2011-11-15

申请号：US12844234

申请日：2010-07-27

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： G11C11/34

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

摘要： A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

摘要翻译： 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

公开(公告)号：US20100289071A1

公开(公告)日：2010-11-18

申请号：US12844234

申请日：2010-07-27

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

摘要： A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

摘要翻译： 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

公开(公告)号：US07791951B2

公开(公告)日：2010-09-07

申请号：US12364570

申请日：2009-02-03

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： G11C11/34

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

摘要： A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

摘要翻译： 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

公开(公告)号：US20090141562A1

公开(公告)日：2009-06-04

申请号：US12364570

申请日：2009-02-03

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： G11C16/06 ,  G11C11/34

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

摘要： A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

摘要翻译： 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。

公开(公告)号：US20090121277A1

公开(公告)日：2009-05-14

申请号：US12289297

申请日：2008-10-24

申请人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L27/11524

摘要： The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer.

摘要翻译： 非易失性存储器件包括半导体衬底和限定半导体衬底中的有源区的器件隔离层。 器件隔离层包括比半导体衬底的顶表面低的顶表面，使得有源区的侧上表面被暴露。 感测线与有源区和器件隔离层交叉，并且与感测线间隔开的字线与有源区和器件隔离层交叉。