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    Narrow-body damascene tri-gate FinFET
    31.
    发明授权
    Narrow-body damascene tri-gate FinFET 有权
    窄体镶嵌三栅极FinFET

    公开(公告)号：US07186599B2

    公开(公告)日：2007-03-06

    申请号：US10754540

    申请日：2004-01-12

    Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

    Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

    IPC: H01L21/00 ,  H01L21/84

    CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in a first pattern over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the first semi-conducting material to leave a trench in the dielectric layer corresponding to the first pattern, thinning a portion of the fin exposed within the trench, and forming a metal gate within the trench.

    Abstract translation: 形成鳍状场效应晶体管的方法包括：在鳍片的第一端上形成翅片并形成源极区域，在鳍片的第二端部形成漏极区域。 该方法还包括在鳍上形成具有第一图案的第一半导体材料的虚拟栅极，并在虚拟栅极周围形成介电层。 该方法还包括去除第一半导体材料以在对应于第一图案的电介质层中留下沟槽，使在沟槽内暴露的鳍片的一部分变薄，并在沟槽内形成金属栅极。

    Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices
    32.
    发明授权
    Planarizing sacrificial oxide to improve gate critical dimension in semiconductor devices 有权
    平面化牺牲氧化物以改善半导体器件中的栅极临界尺寸

    公开(公告)号：US07091068B1

    公开(公告)日：2006-08-15

    申请号：US10310776

    申请日：2002-12-06

    Applicant: Shibly S. Ahmed ,  Cyrus E. Tabery ,  Bin Yu

    Inventor： Shibly S. Ahmed ,  Cyrus E. Tabery ,  Bin Yu

    IPC: H01L21/00

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include forming a sacrificial material over the gate material and planarizing the sacrificial material. An antireflective coating may be deposited on the planarized sacrificial material. A gate structure may then be formed by etching the gate material.

    Abstract translation: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构，并在栅极结构上沉积栅极材料。 该方法还可以包括在栅极材料上形成牺牲材料并平坦化牺牲材料。 可以在平坦化的牺牲材料上沉积抗反射涂层。 然后可以通过蚀刻栅极材料形成栅极结构。

    Narrow body raised source/drain metal gate MOSFET
    33.
    发明授权
    Narrow body raised source/drain metal gate MOSFET 有权
    窄体凸起源极/漏极金属栅极MOSFET

    公开(公告)号：US07034361B1

    公开(公告)日：2006-04-25

    申请号：US10653234

    申请日：2003-09-03

    Applicant: Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

    Inventor： Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

    IPC: H01L27/01

    CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795

    Abstract: A semiconductor device includes a fin, a source region formed adjacent the fin and having a height greater than that of the fin, and a drain region formed adjacent the a second side of the fin and having a height greater than that of the fin. A metal gate region is formed at a top surface and at least one side surface of the fin. A width of the source and drain region may be greater than that of the fin. The semiconductor device may exhibit a reduced series resistance and an improved transistor drive current.

    Abstract translation: 半导体器件包括鳍状物，邻近翅片形成的源极区域，其高度大于鳍状物的高度;以及漏极区域，其形成在翅片的第二侧附近并且具有高于翅片的高度。 金属栅极区域形成在翅片的顶表面和至少一个侧表面处。 源极和漏极区域的宽度可以大于鳍片的宽度。 半导体器件可以呈现减小的串联电阻和改进的晶体管驱动电流。

    System and method for forming stacked fin structure using metal-induced-crystallization
    36.
    发明授权
    System and method for forming stacked fin structure using metal-induced-crystallization 失效
    使用金属诱导结晶形成堆叠鳍结构的系统和方法

    公开(公告)号：US06894337B1

    公开(公告)日：2005-05-17

    申请号：US10768014

    申请日：2004-02-02

    Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

    Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

    IPC: H01L21/20 ,  H01L21/336 ,  H01L27/08 ,  H01L29/786

    CPC classification number: H01L29/785 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02672 ,  H01L21/2022 ,  H01L29/66795 ,  H01L29/7853

    Abstract: A method facilitates the formation of a stacked fin structure for a semiconductor device that includes a substrate. The method includes forming one or more oxide layers on the substrate and forming one or more amorphous silicon layers interspersed with the one or more oxide layers. The method further includes etching the one or more oxide layers and the one or more amorphous silicon layers to form a stacked fin structure and performing a metal-induced crystallization operation to convert the one or more amorphous silicon layers to one or more crystalline silicon layers.

    Abstract translation: 一种方法有助于形成用于包括衬底的半导体器件的堆叠鳍式结构。 该方法包括在衬底上形成一个或多个氧化物层并形成与该一个或多个氧化物层分开的一个或多个非晶硅层。 该方法还包括蚀刻一个或多个氧化物层和一个或多个非晶硅层以形成堆叠鳍状结构，并执行金属诱导结晶操作以将一个或多个非晶硅层转换成一个或多个结晶硅层。

    Damascene finfet gate with selective metal interdiffusion
    37.
    发明授权
    Damascene finfet gate with selective metal interdiffusion 有权
    大马士革finfet门与选择性金属相互扩散

    公开(公告)号：US06855989B1

    公开(公告)日：2005-02-15

    申请号：US10674520

    申请日：2003-10-01

    Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

    Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

    IPC: H01L21/336 ,  H01L27/01 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

    CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795

    Abstract: A fin field effect transistor includes a fin, a source region, a drain region, a first gate electrode and a second gate electrode. The fin includes a channel. The source region is formed adjacent a first end of the fin and the drain region is formed adjacent a second end of the fin. The first gate electrode includes a first layer of metal material formed adjacent the fin. The second gate electrode includes a second layer of metal material formed adjacent the first layer. The first layer of metal material has a different work function than the second layer of metal material. The second layer of metal material selectively diffuses into the first layer of metal material via metal interdiffusion.

    Abstract translation: 翅片场效应晶体管包括鳍片，源极区域，漏极区域，第一栅极电极和第二栅极电极。 鳍包括一个通道。 源区域邻近翅片的第一端形成，并且漏极区域邻近翅片的第二端形成。 第一栅电极包括邻近翅片形成的第一金属材料层。 第二栅电极包括与第一层相邻形成的第二金属材料层。 第一层金属材料具有与第二层金属材料不同的功函数。 金属材料的第二层选择性地通过金属相互扩散扩散到金属材料的第一层中。

    DAISY CHAIN DISTRIBUTION IN DATA CENTERS
    40.
    发明申请
    DAISY CHAIN DISTRIBUTION IN DATA CENTERS 有权
    数据中心的DAISY链分配

    公开(公告)号：US20150286441A1

    公开(公告)日：2015-10-08

    申请号：US14746582

    申请日：2015-06-22

    Applicant: Aswani Kumar Raveendran Nair ,  Sergiy Pereshyvaylo ,  Bin Yu ,  Sudheendra Vasudeva Murthy

    Inventor： Aswani Kumar Raveendran Nair ,  Sergiy Pereshyvaylo ,  Bin Yu ,  Sudheendra Vasudeva Murthy

    IPC: G06F3/06

    CPC classification number: H04L41/0659 ,  G06F11/006 ,  G06F11/0709 ,  G06F11/0727 ,  G06F11/0793 ,  G06F11/1423 ,  G06F17/30194 ,  H04L67/06 ,  H04L67/1097

    Abstract: A method and a system to provide daisy chain distribution in data centers are provided. A node identification module identifies three or more data nodes of a plurality of data nodes. The identification of three or more data nodes indicates that the respective data nodes are to receive a copy of a data file. A connection creation module to, using one or more processors, create communication connections between the three or more data nodes. The communication connections form a daisy chain beginning at a seeder data node of the three or more data nodes and ending at a terminal data node of the three or more data nodes.

    Abstract translation: 提供了一种在数据中心提供菊花链分发的方法和系统。 节点识别模块识别多个数据节点中的三个或多个数据节点。 三个或更多个数据节点的标识指示相应的数据节点要接收数据文件的副本。 连接创建模块，用于使用一个或多个处理器在三个或更多个数据节点之间建立通信连接。 通信连接形成从三个或更多个数据节点的播种器数据节点开始并且结束于三个或更多个数据节点的终端数据节点的菊花链。

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