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    Etch stop layer for etching FinFET gate over a large topography
    4.
    发明授权
    Etch stop layer for etching FinFET gate over a large topography 有权
    蚀刻停止层，用于在大地形上蚀刻FinFET栅极

    公开(公告)号：US06787476B1

    公开(公告)日：2004-09-07

    申请号：US10632989

    申请日：2003-08-04

    申请人： Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Chih-Yuh Yang ,  Bin Yu

    发明人： Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Chih-Yuh Yang ,  Bin Yu

    IPC分类号： H01L21302

    CPC分类号： H01L29/785 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/4908 ,  H01L29/66795

    摘要： A method of forming a gate for a Fin Field Effect Transistor (FinFET) is provided. The method includes forming a first layer of material over a fin and forming a second layer over the first layer. The second layer includes either Ti or TiN. The method further includes forming a third layer over the second layer. The third layer includes an anti-reflective coating. The method also includes etching the first, second and third layers to form the gate for the FinFET.

    摘要翻译： 提供了一种形成Fin场效应晶体管（FinFET）的栅极的方法。 该方法包括在翅片上形成第一层材料，并在第一层上形成第二层。 第二层包括Ti或TiN。 该方法还包括在第二层上形成第三层。 第三层包括抗反射涂层。 该方法还包括蚀刻第一，第二和第三层以形成用于FinFET的栅极。

    Method for forming fins in a FinFET device using sacrificial carbon layer
    7.
    发明授权
    Method for forming fins in a FinFET device using sacrificial carbon layer 有权
    在使用牺牲碳层的FinFET器件中形成翅片的方法

    公开(公告)号：US06645797B1

    公开(公告)日：2003-11-11

    申请号：US10310926

    申请日：2002-12-06

    申请人： Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

    发明人： Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

    IPC分类号： H01L2184

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.

    摘要翻译： 一种在半导体器件中形成翅片的方法，包括：衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电层，包括在导电层上形成碳层，并在碳层上形成掩模 。 该方法还包括蚀刻掩模和碳层以形成至少一种结构，其中结构具有第一宽度，将至少一个结构中的碳层的宽度减小到第二宽度，沉积氧化物层以围绕 至少一个结构，去除所述氧化物层和所述掩模的一部分，除去所述碳层以在所述至少一个结构中的每一个结构的氧化物层的剩余部分中形成开口，用导电材料填充所述至少一个开口 并且去除氧化物层的剩余部分和导电层的一部分以形成翅片。

    Method for determining an anti reflective coating thickness for patterning a thin film semiconductor layer
    9.
    发明授权
    Method for determining an anti reflective coating thickness for patterning a thin film semiconductor layer 有权
    确定用于图案化薄膜半导体层的抗反射涂层厚度的方法

    公开(公告)号：US06599766B1

    公开(公告)日：2003-07-29

    申请号：US10093596

    申请日：2002-03-08

    申请人： Cyrus E. Tabery ,  Chih-Yuh Yang ,  Minh Van Ngo

    发明人： Cyrus E. Tabery ,  Chih-Yuh Yang ,  Minh Van Ngo

    IPC分类号： H01L2100

    CPC分类号： G03F7/091 ,  G02B1/115

    摘要： The invention provides a method of selecting an anti reflective layer thickness for patterning a thin film silicon gate layer over a high K dielectric layer. The method comprises selecting a trial anti reflective layer thickness. A first coherent illumination intensity reflected from an interface between the photoresist layer and the anti reflective layer is calculated at the lithography wavelength. A second coherent illumination intensity reflected from an interface between the anti reflective layer and the polysilicon layer is calculated at the lithography wavelength. And, a third coherent illumination intensity reflected from an interface between the polysilicon layer and the high K dielectric layer is calculated at the lithography wavelength. A total coherent illumination intensity that comprises the sum of the first coherent illumination intensity, the second coherent illumination intensity, and the third coherent illumination intensity is calculated and compared to a predetermined threshold. If below the threshold, the trail anti reflective layer thickness is selected as the anti reflective layer thickness.

    摘要翻译： 本发明提供一种选择抗反射层厚度以在高K电介质层上图案化薄膜硅栅极层的方法。 该方法包括选择试验抗反射层厚度。 在光刻波长处计算从光致抗蚀剂层和抗反射层之间的界面反射的第一相干照明强度。 在光刻波长处计算从抗反射层和多晶硅层之间的界面反射的第二相干照明强度。 并且，在光刻波长处计算从多晶硅层和高K电介质层之间的界面反射的第三相干照明强度。 计算包括第一相干照明强度，第二相干照射强度和第三相干照明强度的总和的总相干照明强度并将其与预定阈值进行比较。 如果低于阈值，则选择防反射层厚度作为抗反射层厚度。

    Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal
    10.
    发明授权
    Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal 有权
    包括高K栅极电介质的晶体管栅极的制造工艺，其具有原位抗蚀剂修整，栅极蚀刻和高K电介质去除

    公开(公告)号：US06790782B1

    公开(公告)日：2004-09-14

    申请号：US10157450

    申请日：2002-05-29

    申请人： Chih-Yuh Yang ,  Cyrus E. Tabery ,  Ming-Ren Lin

    发明人： Chih-Yuh Yang ,  Cyrus E. Tabery ,  Ming-Ren Lin

    IPC分类号： H01L21302

    CPC分类号： H01L21/28123 ,  H01L21/0337 ,  H01L21/28273 ,  H01L29/517

    摘要： The invention provides a method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack etch, and removal of exposed regions of the high-K dielectric to be performed efficiently in a single etch chamber. As such, process complexity and processing costs are reduced while throughput and overall process efficiency is improved. The method includes fabricating a high-K gate dielectric etch stop dielectric layer on the surface of a silicon substrate to protect the silicon substrate from erosion during an etch step and to prove a gate dielectric. A polysilicon layer is fabricated above the high-K dielectric layer. An anti-reflective coating layer above the polysilicon layer, and a mask is fabricated above the anti-reflective coating layer to define a gate region and an erosion region. The sequence of etching steps discussed above are performed in-situ in an enclosed high density plasma etching chamber environment.

    摘要翻译： 本发明提供了在高K栅极电介质的表面上形成小几何形状的栅极的方法。 该方法提供了处理步骤，其包括在单个蚀刻室中有效执行的栅极图案修整，栅极堆叠蚀刻和去除高K电介质的暴露区域。 因此，降低了处理复杂性和处理成本，同时提高了吞吐量和整体处理效率。 该方法包括在硅衬底的表面上制造高K栅电介质蚀刻阻挡介电层，以在蚀刻步骤期间保护硅衬底免受腐蚀并证明栅极电介质。 在高K电介质层上方制造多晶硅层。 在多晶硅层上方的抗反射涂层和在抗反射涂层上方制造掩模以限定栅极区域和侵蚀区域。 上述蚀刻步骤的顺序在封闭的高密度等离子体蚀刻室环境中原位进行。