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公开(公告)号：US6150696A
公开(公告)日：2000-11-21
申请号：US55903
申请日：1998-04-07
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.
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32.发明授权Method of manufacturing semiconductor device having impurity region under isolation region 有权制造在隔离区域具有杂质区域的半导体器件的制造方法公开(公告)号：US07556997B2
公开(公告)日：2009-07-07
申请号：US11907864
申请日：2007-10-18
IPC分类号： H01L21/8238
CPC分类号： H01L29/78615 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
摘要翻译： 在形成NMOS晶体管的源极/漏极区域中，N +块抗蚀剂膜51中的N +块区域41的栅极延伸区域<41a>防止位于栅极下方的阱区域11 从N型杂质的注入开始的方向延伸区域41a。 可以形成具有在栅电极9的纵向延伸上注入N型杂质的可能性的具有高电阻形成区域
的高电阻形成区域， 比传统的高电阻形成区域 。 因此，获得具有能够降低体电阻的部分隔离体固定的SOI结构的半导体器件及其制造方法。 -
33.发明授权Semiconductor device having a trench isolation and method of fabricating the same 失效具有沟槽隔离的半导体器件及其制造方法公开(公告)号：US07494883B2
公开(公告)日：2009-02-24
申请号：US11543213
申请日：2006-10-05
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60〜120keV，通道阻挡层的密度为1×10 17〜1×10 19 / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。
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34.发明授权Method of manufacturing semiconductor device having impurity region under isolation region 失效制造在隔离区域具有杂质区域的半导体器件的制造方法公开(公告)号：US07470582B2
公开(公告)日：2008-12-30
申请号：US11907857
申请日：2007-10-18
IPC分类号： H01L21/8238
CPC分类号： H01L29/78615 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
摘要翻译： 在形成NMOS晶体管的源极/漏极区域中，N +块抗蚀剂膜51中的N +块区域41的栅极延伸区域<41a>防止位于栅极下方的阱区域11 从N型杂质的注入开始的方向延伸区域41a。 可以形成具有在栅电极9的纵向延伸上注入N型杂质的可能性的具有高电阻形成区域
的高电阻形成区域， 比传统的高电阻形成区域 。 因此，获得具有能够降低体电阻的部分隔离体固定SOI结构的半导体器件及其制造方法。 -
35.发明申请Method of manufacturing semiconductor device having impurity region under isolation region 有权制造在隔离区域具有杂质区域的半导体器件的制造方法公开(公告)号：US20070034952A1
公开(公告)日：2007-02-15
申请号：US11493529
申请日：2006-07-27
CPC分类号： H01L29/78615 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
摘要翻译： 在形成NMOS晶体管的源极/漏极区域的情况下，在N + +块区域中的N + +块区域<41>的栅极方向延伸区域 抗蚀剂膜<51>防止位于栅极方向延伸区域41a之下的阱区11注入N型杂质。 作为高电阻形成区域，其是具有在栅电极9的纵向延伸上注入N型杂质的可能性的阱区域11，可以形成为高电阻形成区域 比传统的高电阻形成区域窄。 因此，获得具有能够降低体电阻的部分隔离体固定的SOI结构的半导体器件及其制造方法。
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36.发明申请Semiconductor device having a trench isolation and method of fabricating the same 失效具有沟槽隔离的半导体器件及其制造方法公开(公告)号：US20050101091A1
公开(公告)日：2005-05-12
申请号：US11011655
申请日：2004-12-15
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L21/84 , H01L27/08 , H01L27/12 , H01L29/786 , H01L21/8242 , H01L21/8234
CPC分类号： H01L21/2652 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60至120keV，并且通道阻挡层的密度设定为1×10 17至1×10 19 / SUP> / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。
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37.发明授权Semiconductor device having a trench isolation and method of fabricating the same 失效具有沟槽隔离的半导体器件及其制造方法公开(公告)号：US06875663B2
公开(公告)日：2005-04-05
申请号：US10237022
申请日：2002-09-09
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L21/84 , H01L27/08 , H01L27/12 , H01L29/786
CPC分类号： H01L21/2652 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60至120keV，并且通道阻挡层的密度设定为1×10 17至1×10 19 / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。
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公开(公告)号：US06794717B2
公开(公告)日：2004-09-21
申请号：US09986004
申请日：2001-11-07
IPC分类号： H01L2701
CPC分类号： H01L29/78615 , H01L21/76264 , H01L21/84 , H01L27/11 , H01L27/1112 , H01L27/1203 , H01L29/66772 , H01L29/78654 , Y10S257/904
摘要： It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “-” functions as a gate electrode of an original MOS transistor.
摘要翻译： 本发明的目的是提供具有SOI结构的半导体器件，其中可以以高稳定性固定由部分隔离区隔离的元件形成区域中的体区的电位。 在由部分氧化膜（31）隔离的元件形成区域中形成包括源极区（51），漏极区（61）和H栅电极（71）的MOS晶体管。 H栅电极（71）将从栅极宽度W方向形成的主体区域（13）与漏极区域（61）和源极区域（51）的源极区域（51）和漏极区域（61）相邻地隔离 ）通过“I”横向（图中的垂直方向），中心“ - ”用作原始MOS晶体管的栅电极。
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公开(公告)号：US07183167B2
公开(公告)日：2007-02-27
申请号：US11011655
申请日：2004-12-15
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
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40.发明申请MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable thickness 失效具有体接触的SOI衬底上的MOS晶体管和具有可变厚度的栅极绝缘膜公开(公告)号：US20060134843A1
公开(公告)日：2006-06-22
申请号：US11317687
申请日：2005-12-27
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7841 , H01L29/78615 , H01L29/78654 , Y10S438/981
摘要： It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.
摘要翻译： 本发明的目的是提供一种能够进行身体固定并实现快速且稳定的操作的SOI装置。 在栅极（12）的栅极接触焊盘（GP）与SOI层（3）之间的部分之间设置厚度为1〜5nm的栅极绝缘膜（11）和栅极绝缘膜（ 在栅极接触焊盘（GP）和SOI层（3）之间设置有厚度为5〜15nm的光栅（110）。 连续设置栅极绝缘膜（11）和栅极绝缘膜（110）。
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