公开(公告)号：US07301369B2

公开(公告)日：2007-11-27

申请号：US11387872

申请日：2006-03-24

申请人： Shinichi Kanno ,  Toshikatsu Hida

发明人： Shinichi Kanno ,  Toshikatsu Hida

IPC分类号： G06F7/38 ,  H01L25/00

CPC分类号： H03K19/17776

摘要： A programmable gate array apparatus includes macrocells connected in series, each macrocell including first group of storage elements in which active context data item is stored and second group of storage elements corresponding to storage elements of first group respectively, in which idle context data item is stored, connects storage elements of second group in series, loads context data item into second group whose storage elements are connected in series, connects first group and second group by connecting storage elements of first group to corresponding storage elements of second group respectively, and swaps context data items between first group and second group.

摘要翻译： 可编程门阵列装置包括串联连接的宏小区，每个宏小区包括其中存储有活动上下文数据项的第一组存储单元和对应于第一组存储单元的第二组存储单元，其中存储空闲上下文数据项 将第二组的存储元件串联连接，将上下文数据项加载到其存储元件串联连接的第二组中，通过将第一组的存储元件分别连接到第二组的相应存储元件，并将交换上下文 第一组与第二组之间的数据项。

公开(公告)号：US09331713B2

公开(公告)日：2016-05-03

申请号：US13600929

申请日：2012-08-31

申请人： Yoshiki Saito ,  Shinichi Kanno ,  Toshikatsu Hida

发明人： Yoshiki Saito ,  Shinichi Kanno ,  Toshikatsu Hida

IPC分类号： H03M13/05 ,  H03M13/00

CPC分类号： H03M13/05 ,  H03M13/6516

摘要： According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit.

摘要翻译： 根据实施例，一种编码装置包括：配置为保存参数的参数保持单元; 错误检测码保持单元，被配置为保存从该参数生成的检错码; 错误检测单元，被配置为使用保持在错误检测码保持单元中的检错码来检测保存在参数保持单元中的参数中的错误; 错误校正单元，被配置为校正由所述错误检测单元检测到的所述错误; 选择单元，被配置为通过误差校正单元选择已经经过纠错的参数; 以及编码单元，被配置为使用由所述选择单元选择的参数来对数据进行编码。

公开(公告)号：US20070115150A1

公开(公告)日：2007-05-24

申请号：US11387872

申请日：2006-03-24

申请人： Shinichi Kanno ,  Toshikatsu Hida

发明人： Shinichi Kanno ,  Toshikatsu Hida

IPC分类号： H03M7/00

CPC分类号： H03K19/17776

摘要： A programmable gate array apparatus includes macrocells connected in series, each macrocell including first group of storage elements in which active context data item is stored and second group of storage elements corresponding to storage elements of first group respectively, in which idle context data item is stored, connects storage elements of second group in series, loads context data item into second group whose storage elements are connected in series, connects first group and second group by connecting storage elements of first group to corresponding storage elements of second group respectively, and swaps context data items between first group and second group.

公开(公告)号：US09164831B2

公开(公告)日：2015-10-20

申请号：US14234856

申请日：2012-03-14

申请人： Koji Horisaki ,  Toshikatsu Hida ,  Shinichi Kanno ,  Osamu Torii

发明人： Koji Horisaki ,  Toshikatsu Hida ,  Shinichi Kanno ,  Osamu Torii

IPC分类号： H03M13/00 ,  G06F11/10 ,  H03M13/15

CPC分类号： G06F11/1044 ,  G06F11/1048 ,  H03M13/1575

摘要： According to an embodiment, a memory interface that includes n number of channels and writes data subjected to an error correction encoding process having capable of correcting t symbols, n number of first error correction decoding units that perform an error correction decoding process of correcting s (s

摘要翻译： 根据实施例，一种存储器接口，其包括n个通道并且写入经过可纠正t个符号的纠错编码处理的数据，n个第一纠错解码单元执行纠错解码处理 s

公开(公告)号：US20140173377A1

公开(公告)日：2014-06-19

申请号：US14234856

申请日：2012-03-14

申请人： Koji Horisaki ,  Toshikatsu Hida ,  Shinichi Kanno ,  Osamu Torii

发明人： Koji Horisaki ,  Toshikatsu Hida ,  Shinichi Kanno ,  Osamu Torii

IPC分类号： G06F11/10

CPC分类号： G06F11/1044 ,  G06F11/1048 ,  H03M13/1575

摘要： According to an embodiment, a memory interface that includes n number of channels and writes data subjected to an error correction encoding process having capable of correcting t symbols, n number of first error correction decoding units that perform an error correction decoding process of correcting s (s

摘要翻译： 根据实施例，一种存储器接口，其包括n个通道并且写入经过可纠正t个符号的纠错编码处理的数据，n个第一纠错解码单元执行纠错解码处理 s

公开(公告)号：US08549388B2

公开(公告)日：2013-10-01

申请号：US13035194

申请日：2011-02-25

申请人： Kazuhiro Fukutomi ,  Hiroshi Yao ,  Shinichi Kanno ,  Shigehiro Asano ,  Toshikatsu Hida ,  Yasuhiro Kimura

发明人： Kazuhiro Fukutomi ,  Hiroshi Yao ,  Shinichi Kanno ,  Shigehiro Asano ,  Toshikatsu Hida ,  Yasuhiro Kimura

IPC分类号： H03M13/00

CPC分类号： G06F11/108 ,  G06F2211/1059 ,  G06F2211/1073 ,  G06F2211/1092

摘要： According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.

摘要翻译： 根据一个实施例，控制器控制对包括第一数据存储单元和第二数据存储单元的存储装置的写入和读取。 第二数据存储单元存储用户数据和用户数据的奇偶校验数据。 第一数据存储单元存储奇偶校验数据。 控制器包括奇偶校验更新单元和奇偶校验写入单元。 当更新奇偶校验数据时，奇偶校验更新单元将更新的奇偶校验数据写入第一数据存储单元。 当满足特定要求时，奇偶写入单元读取写入第一数据存储单元中的奇偶校验数据，并将读出的奇偶校验数据写入第二数据存储单元。

公开(公告)号：US07432735B2

公开(公告)日：2008-10-07

申请号：US11874981

申请日：2007-10-19

申请人： Shinichi Kanno ,  Toshikatsu Hida

发明人： Shinichi Kanno ,  Toshikatsu Hida

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17776

摘要： A programmable gate array apparatus includes macrocells connected in series, each macrocell including first group of storage elements in which active context data item is stored and second group of storage elements corresponding to storage elements of first group respectively, in which idle context data item is stored, connects storage elements of second group in series, loads context data item into second group whose storage elements are connected in series, connects first group and second group by connecting storage elements of first group to corresponding storage elements of second group respectively, and swaps context data items between first group and second group.

摘要翻译： 可编程门阵列装置包括串联连接的宏小区，每个宏小区包括其中存储有活动上下文数据项的第一组存储单元和对应于第一组存储单元的第二组存储单元，其中存储空闲上下文数据项 将第二组的存储元件串联连接，将上下文数据项加载到其存储元件串联连接的第二组中，通过将第一组的存储元件分别连接到第二组的相应存储元件，并将交换上下文 第一组与第二组之间的数据项。

公开(公告)号：US20100169553A1

公开(公告)日：2010-07-01

申请号：US12566236

申请日：2009-09-24

申请人： Hirokuni YANO ,  Shinichi Kanno

发明人： Hirokuni YANO ,  Shinichi Kanno

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F2212/7202

摘要： A memory system according to an embodiment of the present invention includes a volatile first storing unit, a nonvolatile second storing unit, a controller that transfers data between a host apparatus and the second storing unit via the first storing unit. The memory system monitors whether data written from the host apparatus in the first storing unit has a specific pattern in management units. When data to be flushed to the second storing unit has the specific pattern, the memory system set an invalid address value that is not in use in the second storing unit to the data.

摘要翻译： 根据本发明的实施例的存储器系统包括易失性第一存储单元，非易失性第二存储单元，经由第一存储单元在主机设备和第二存储单元之间传送数据的控制器。 存储系统监视从第一存储单元中的主机设备写入的数据是否具有管理单元中的特定模式。 当要刷新到第二存储单元的数据具有特定模式时，存储器系统将不在第二存储单元中使用的无效地址值设置为数据。

公开(公告)号：US08327065B2

公开(公告)日：2012-12-04

申请号：US12566236

申请日：2009-09-24

申请人： Hirokuni Yano ,  Shinichi Kanno

发明人： Hirokuni Yano ,  Shinichi Kanno

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F2212/7202

摘要： A memory system according to an embodiment of the present invention includes a volatile first storing unit, a nonvolatile second storing unit, a controller that transfers data between a host apparatus and the second storing unit via the first storing unit. The memory system monitors whether data written from the host apparatus in the first storing unit has a specific pattern in management units. When data to be flushed to the second storing unit has the specific pattern, the memory system set an invalid address value that is not in use in the second storing unit to the data.

摘要翻译： 根据本发明的实施例的存储器系统包括易失性第一存储单元，非易失性第二存储单元，经由第一存储单元在主机设备和第二存储单元之间传送数据的控制器。 存储系统监视从第一存储单元中的主机设备写入的数据是否具有管理单元中的特定模式。 当要刷新到第二存储单元的数据具有特定模式时，存储器系统将不在第二存储单元中使用的无效地址值设置为数据。

公开(公告)号：US08611154B2

公开(公告)日：2013-12-17

申请号：US12866668

申请日：2008-09-22

申请人： Shigehiro Asano ,  Shinichi Kanno ,  Junji Yano

发明人： Shigehiro Asano ,  Shinichi Kanno ,  Junji Yano

IPC分类号： G11C11/34

CPC分类号： H01L23/5228 ,  G06F9/4401 ,  G11C5/005 ,  G11C5/04 ,  G11C5/066 ,  G11C16/0408 ,  H01L23/60 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m semiconductor chips CP1 to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP1 to CPm.

摘要翻译： 在单个半导体封装PK1上安装半导体芯片CP1至CPm，并且半导体封装PK1具有由m个半导体芯片CP1至CPm的m个焊盘电极PD1至PDm共享的外部端子T. 静电保护电路CD仅安装在m个半导体芯片CP1至CPm的一个CPm上。