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122 条记录 (耗时 0.035 秒)

    Storage device
    1.
    发明授权
    Storage device 失效
    储存设备

    公开(公告)号：US08640013B2

    公开(公告)日：2014-01-28

    申请号：US13601707

    申请日：2012-08-31

    申请人： Toshikatsu Hida ,  Shinichi Kanno ,  Osamu Torii ,  Koji Horisaki ,  Dong Zhang

    发明人： Toshikatsu Hida ,  Shinichi Kanno ,  Osamu Torii ,  Koji Horisaki ,  Dong Zhang

    IPC分类号： H03M13/15

    CPC分类号： G06F11/10 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/159 ,  H03M13/3715 ,  H03M13/3746

    摘要： According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.

    摘要翻译： 根据一个实施例，存储装置执行最大校正性能为T比特的代码的纠错处理，所述解码装置包括纠错处理器，用于使用能够处理J比特错误的计算装置（J 是等于或大于1且小于T的整数），其中错误数量期望值的初始值被设置为I（I是等于或大于1且小于T的整数），并且执行增量 的误差数量期望值和纠错处理的执行被重复，直到没有检测到错误或者错误数量期望值变为T位为止。

    ENCODING APPARATUS, CONTROL METHOD OF ENCODING APPARATUS, AND MEMORY DEVICE
    2.
    发明申请
    ENCODING APPARATUS, CONTROL METHOD OF ENCODING APPARATUS, AND MEMORY DEVICE 有权
    编码装置，编码装置的控制方法和存储装置

    公开(公告)号：US20130254637A1

    公开(公告)日：2013-09-26

    申请号：US13600929

    申请日：2012-08-31

    申请人： Yoshiki Saito ,  Shinichi Kanno ,  Toshikatsu Hida

    发明人： Yoshiki Saito ,  Shinichi Kanno ,  Toshikatsu Hida

    IPC分类号： H03M13/05

    CPC分类号： H03M13/05 ,  H03M13/6516

    摘要： According to an embodiment, an encoding apparatus includes a parameter holding unit configured to hold a parameter; an error-detecting code holding unit configured to hold an error-detecting code that is generated from the parameter; an error detecting unit configured to detect an error in the parameter, which is held in the parameter holding unit, with the use of the error-detecting code held in the error-detecting code holding unit; an error correcting unit configured to correct the error detected by the error detecting unit; a selecting unit configured to select the parameter that has been subjected to error correction by the error correcting unit; and an encoding unit configured to encode data with the use of the parameter selected by the selecting unit.

    摘要翻译： 根据实施例，一种编码装置包括：配置为保存参数的参数保持单元; 错误检测码保持单元，被配置为保存从该参数生成的检错码; 错误检测单元，被配置为使用保持在错误检测码保持单元中的检错码来检测保存在参数保持单元中的参数中的错误; 错误校正单元，被配置为校正由所述错误检测单元检测到的所述错误; 选择单元，被配置为通过误差校正单元选择已经经过纠错的参数; 以及编码单元，被配置为使用由所述选择单元选择的参数来对数据进行编码。

    CONTROLLER, STORAGE APPARATUS, AND COMPUTER PROGRAM PRODUCT
    3.
    发明申请
    CONTROLLER, STORAGE APPARATUS, AND COMPUTER PROGRAM PRODUCT 有权
    控制器，存储设备和计算机程序产品

    公开(公告)号：US20120072811A1

    公开(公告)日：2012-03-22

    申请号：US13035194

    申请日：2011-02-25

    申请人： Kazuhiro FUKUTOMI ,  Hiroshi Yao ,  Shinichi Kanno ,  Shigehiro Asano ,  Toshikatsu Hida ,  Yasuhiro Kimura

    发明人： Kazuhiro FUKUTOMI ,  Hiroshi Yao ,  Shinichi Kanno ,  Shigehiro Asano ,  Toshikatsu Hida ,  Yasuhiro Kimura

    IPC分类号： H03M13/09 ,  G06F11/10

    CPC分类号： G06F11/108 ,  G06F2211/1059 ,  G06F2211/1073 ,  G06F2211/1092

    摘要： According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.

    摘要翻译： 根据一个实施例，控制器控制对包括第一数据存储单元和第二数据存储单元的存储装置的写入和读取。 第二数据存储单元存储用户数据和用户数据的奇偶校验数据。 第一数据存储单元存储奇偶校验数据。 控制器包括奇偶校验更新单元和奇偶校验写入单元。 当更新奇偶校验数据时，奇偶校验更新单元将更新的奇偶校验数据写入第一数据存储单元。 当满足特定要求时，奇偶写入单元读取写入第一数据存储单元中的奇偶校验数据，并将读出的奇偶校验数据写入第二数据存储单元。

    Memory system and control method thereof
    5.
    发明授权
    Memory system and control method thereof 有权
    存储系统及其控制方法

    公开(公告)号：US07958411B2

    公开(公告)日：2011-06-07

    申请号：US12551213

    申请日：2009-08-31

    申请人： Shinichi Kanno ,  Hirokuni Yano ,  Toshikatsu Hida ,  Kazuya Kitsunai ,  Junji Yano

    发明人： Shinichi Kanno ,  Hirokuni Yano ,  Toshikatsu Hida ,  Kazuya Kitsunai ,  Junji Yano

    IPC分类号： G11C29/00 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G11C16/349 ,  G06F11/1068 ,  G06F12/0246 ,  G06F2212/7211 ,  G11C16/16 ,  G11C29/76

    摘要： A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.

    摘要翻译： 一种存储器系统，包括：包括作为数据擦除单元的块的非易失性存储器，测量擦除每个块中的数据的擦除时间的测量单元;具有块表的块控制器，其将指示空闲状态之一的状态值和 具有每个块的擦除时间的使用状态，检测在短时间内共同发生重写的块的检测器，选择具有旧擦除时间的空闲块作为第一块的第一选择器，选择 如果第一块被包括在由检测器检测到的块中，则将具有旧擦除时间的块用作第二块，以及调平单元，其将第二块中的数据移动到第一块。

    MEMORY SYSTEM
    9.
    发明申请
    MEMORY SYSTEM 审中-公开
    记忆系统

    公开(公告)号：US20090222628A1

    公开(公告)日：2009-09-03

    申请号：US12394934

    申请日：2009-02-27

    申请人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda ,  Shinichi Kanno ,  Toshikatsu Hida

    发明人： Junji Yano ,  Hidenori Matsuzaki ,  Kosuke Hatsuda ,  Shinichi Kanno ,  Toshikatsu Hida

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0868 ,  G06F12/0804 ,  G06F12/0897 ,  G06F2212/214

    摘要： A controller determines whether data stored in a first storing area should be flushed to a second storing area or a third storing area. When flushing of data in a track unit from at least one of the first storing area and the second storing area unit to the third storing area unit is determined, the controller collects data included in the flushed data in the track unit from at least one of the first storing area and the second storing area including the storing area from which the flushing of the data is determined, merges the flushed data and the collected data, and writes the merged data in the third storing area.

    摘要翻译： 控制器确定存储在第一存储区域中的数据是否应被刷新到第二存储区域或第三存储区域。 当从第一存储区域和第二存储区域单元中的至少一个到第三存储区域单元将轨道单元中的数据刷新确定时，控制器从包括在轨道单元中的冲洗数据中的数据从 第一存储区域和第二存储区域包括确定了冲洗数据的存储区域，并且将刷新的数据和收集的数据合并，并将合并的数据写入第三存储区域。

    Programmable gate array apparatus and method for switching circuits
    10.
    发明授权
    Programmable gate array apparatus and method for switching circuits 失效
    用于开关电路的可编程门阵列装置和方法

    公开(公告)号：US07301369B2

    公开(公告)日：2007-11-27

    申请号：US11387872

    申请日：2006-03-24

    申请人： Shinichi Kanno ,  Toshikatsu Hida

    发明人： Shinichi Kanno ,  Toshikatsu Hida

    IPC分类号： G06F7/38 ,  H01L25/00

    CPC分类号： H03K19/17776

    摘要： A programmable gate array apparatus includes macrocells connected in series, each macrocell including first group of storage elements in which active context data item is stored and second group of storage elements corresponding to storage elements of first group respectively, in which idle context data item is stored, connects storage elements of second group in series, loads context data item into second group whose storage elements are connected in series, connects first group and second group by connecting storage elements of first group to corresponding storage elements of second group respectively, and swaps context data items between first group and second group.

    摘要翻译： 可编程门阵列装置包括串联连接的宏小区，每个宏小区包括其中存储有活动上下文数据项的第一组存储单元和对应于第一组存储单元的第二组存储单元，其中存储空闲上下文数据项 将第二组的存储元件串联连接，将上下文数据项加载到其存储元件串联连接的第二组中，通过将第一组的存储元件分别连接到第二组的相应存储元件，并将交换上下文 第一组与第二组之间的数据项。