Electronic device
    31.
    发明授权
    Electronic device 失效
    电子设备

    公开(公告)号:US6014132A

    公开(公告)日:2000-01-11

    申请号:US173864

    申请日:1993-12-23

    摘要: An electronic device for entering information comprises a CPU for controlling the entire electronic device, information entry means for obtaining information at a predetermined time interval, and control means for controlling the CPU and the information input means such that, in a first mode in which no information is entered, the predetermined time interval is maintained in preparation for sudden entry of information and an operating clock frequency of the CPU is kept at a low frequency, and in a second mode in which information is entered, the predetermined time interval is maintained and the operating clock frequency of the CPU is kept at a high frequency.

    摘要翻译: 用于输入信息的电子设备包括用于控制整个电子设备的CPU,用于以预定时间间隔获得信息的信息输入装置,以及用于控制CPU和信息输入装置的控制装置,使得在第一模式中, 信息被输入,保持预定的时间间隔以准备突然输入信息,并且CPU的操作时钟频率保持在低频,并且在输入信息的第二模式中,保持预定时间间隔,并且 CPU的工作时钟频率保持在高频。

    Method and system utilizing a negotiation phase to transfer commands and
data in separate modes over a host/peripheral interface
    32.
    发明授权
    Method and system utilizing a negotiation phase to transfer commands and data in separate modes over a host/peripheral interface 失效
    方法和系统利用协商阶段通过主机/外设接口以分开的模式传输命令和数据

    公开(公告)号:US5926650A

    公开(公告)日:1999-07-20

    申请号:US661565

    申请日:1996-06-11

    IPC分类号: G06F13/38 G06F13/42

    CPC分类号: G06F13/4221 G06F2213/0004

    摘要: A command information transfer method and system capable of transferring command information by discriminating it from data information, and capable of using protocols of IEEE P1284, when a nibble or byte mode is incorporated which is stipulated by IEEE P1284 as bi-directional parallel I/F. A new communication mode simulating the extensibility link is set by an extensibility request value undefined by IEEE P1284 and command information is transferred at the second and following bytes of such multiple-byte negotiation. An nFault signal is used for both a notice of error and for a reverse direction information transfer request.

    摘要翻译: 一种命令信息传送方法和系统,其能够通过从数据信息中识别命令信息并且能够使用IEEE P1284的协议,当IEEE P1284规定的半字节或字节模式作为双向并行I / F 。 通过由IEEE P1284未定义的扩展请求值来设置模拟可扩展性链路的新的通信模式,并且在这种多字节协商的第二个和后续字节处传送命令信息。 nFault信号用于错误通知和反向信息传输请求。

    Communication control method and apparatus
    33.
    发明授权
    Communication control method and apparatus 失效
    通信控制方法和装置

    公开(公告)号:US5526161A

    公开(公告)日:1996-06-11

    申请号:US262274

    申请日:1994-06-20

    CPC分类号: H04B10/1143

    摘要: A communication apparatus transmits a test message in one direction by the transmitting unit having narrow directivity capable of changing the transmitting direction, and an indication message which indicates that the test message is being transmitted by a transmitting unit having non directivity. Accordingly, the indication message is transmitted at least to the communicating party's apparatus. Subsequently, the transmitting direction of the test message is sequentially changed, and a similar process is performed. When the communicating party's apparatus detects a reception of the indication message, information indicating a level of the test message is transmitted to the transmitting apparatus as a response. The communication apparatus at the transmitting side detects the direction where the communicating party exists by receiving the information indicating the level. Hereinafter, the information communication is performed to adjust the transmitting unit of narrow directivity to the determined direction.

    摘要翻译: 通信装置通过具有能够改变发送方向的窄方向性的发送单元向一个方向发送测试消息,以及指示由具有非方向性的发送单元正在发送测试消息的指示消息。 因此,指示消息至少传送到通信方的装置。 随后,测试消息的发送方向被顺序地改变,并且执行类似的处理。 当通信方的装置检测到指示消息的接收时,作为响应将指示测试消息的级别的信息作为响应发送到发送装置。 发送侧的通信装置通过接收表示电平的信息来检测通信方存在的方向。 在下文中,执行信息通信以将指向性的发送单位调整到确定的方向。

    Memory control device
    34.
    发明授权
    Memory control device 失效
    内存控制装置

    公开(公告)号:US5477490A

    公开(公告)日:1995-12-19

    申请号:US289259

    申请日:1994-08-11

    CPC分类号: G11C7/00

    摘要: An elastic memory determines an amount of delay of input data relative to other input data according to a phase difference between synchronous pulses each indicating a header of a frame of the associated input data. The elastic memory thus synchronizes both input data in the channel level. Both input data are time-division multiplied by a first multiplier. On the other hand, each counter receives synchronous pulses and thereby counting up to make a ROM produce address value of which order is determined previously according to the counted value. These address values are multiplied by a second multiplier. A decoder controls a RAM, a high-impedance control unit and a flip-flop to write in and read out of the RAM the input data. The read data are divided by a signal restoring device.

    摘要翻译: 弹性存储器根据同步脉冲之间的相位差确定输入数据相对于其他输入数据的延迟量,每个同步脉冲指示相关联的输入数据的帧的标题。 因此,弹性存储器使得信道级别中的两个输入数据同步。 两个输入数据都是时分乘以第一乘法器。 另一方面,每个计数器接收同步脉冲,从而向上计数,使得ROM根据计数值产生先前确定了顺序的地址值。 这些地址值乘以第二乘法器。 解码器控制RAM,高阻抗控制单元和触发器来写入和读出RAM中的输入数据。 读取的数据由信号恢复装置分割。