公开(公告)号：US20240020012A1

公开(公告)日：2024-01-18

申请号：US18203901

申请日：2023-05-31

Applicant: SiFive, Inc.

Inventor： Eric Andrew Gouldey ,  Wesley Waylon Terpstra ,  Andrew Waterman

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A processor core may include circuitry that fetches a first instruction followed by a second instruction. The first instruction may be configured to cause a first memory request, and the second instruction may be configured to cause a second memory request. The circuitry may determine that the first memory request is a candidate for combination with the second memory request. Responsive to the determination, the circuitry may send an indication, from the processor core via a bus, that the first memory request is a candidate for combination.

公开(公告)号：US20230237217A1

公开(公告)日：2023-07-27

申请号：US18123422

申请日：2023-03-20

Applicant: SiFive, Inc.

Inventor： Yunsup Lee ,  Richard Xia ,  Derek Pappas ,  Mark Nugent ,  Henry Cook ,  Wesley Waylon Terpstra ,  Pin Hung Chen

IPC: G06F30/20 ,  G06F30/30

CPC classification number: G06F30/20 ,  G06F30/30

Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

公开(公告)号：US11467961B2

公开(公告)日：2022-10-11

申请号：US17332286

申请日：2021-05-27

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Wesley Waylon Terpstra ,  Henry Cook

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/128

Abstract: Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

公开(公告)号：US11321511B2

公开(公告)日：2022-05-03

申请号：US17157564

申请日：2021-01-25

Applicant: SiFive, Inc.

Inventor： Henry Cook ,  Ernest L. Edgar ,  Ryan Macdonald ,  Wesley Waylon Terpstra

IPC: G06F30/327 ,  G06F30/333 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/396 ,  G06F30/398 ,  G06F119/12 ,  G06F115/02

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

公开(公告)号：US20210365609A1

公开(公告)日：2021-11-25

申请号：US17361238

申请日：2021-06-28

Applicant: SiFive, Inc.

Inventor： Yunsup Lee ,  Richard Xia ,  Derek Pappas ,  Mark Nugent ,  Henry Cook ,  Wesley Waylon Terpstra ,  Pin Hung Chen

IPC: G06F30/20 ,  G06F30/30

Abstract: Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.

公开(公告)号：US20210157728A1

公开(公告)日：2021-05-27

申请号：US17103856

申请日：2020-11-24

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra

IPC: G06F12/0811 ,  G06F12/0882 ,  G06F12/0846 ,  G06F12/02

Abstract: Systems and methods are disclosed for virtualized caches. For example, an integrated circuit (e.g., a processor) for executing instructions includes a virtually indexed physically tagged first-level (L1) cache configured to output to an outer memory system one or more bits of a virtual index of a cache access as one or more bits of a requestor identifier. For example, the L1 cache may be configured to operate as multiple logical L1 caches with a cache way of a size less than or equal to a virtual memory page size. For example, the integrated circuit may include an L2 cache of the outer memory system that is configured to receive the requestor identifier and implement a cache coherency protocol to disambiguate an L1 synonym occurring in multiple portions of the virtually indexed physically tagged L1 cache associated with different requestor identifier values.

公开(公告)号：US10902171B1

公开(公告)日：2021-01-26

申请号：US16506507

申请日：2019-07-09

Applicant: SiFive, Inc.

Inventor： Henry Cook ,  Wesley Waylon Terpstra ,  Ryan Macdonald

IPC: G06F17/50 ,  G06F30/39 ,  G06F1/08 ,  G06F30/396 ,  G06F113/18 ,  G06F115/10 ,  G06F30/373 ,  G06F30/327 ,  G06F30/337 ,  G06F30/398 ,  G06F30/3315 ,  G06F30/3312

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. For example, implicit classes may be used to generate clock crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

公开(公告)号：US12271309B2

公开(公告)日：2025-04-08

申请号：US18527181

申请日：2023-12-01

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra

IPC: G06F12/08 ,  G06F12/0802

Abstract: Systems and techniques are disclosed for relative age tracking for entries in a buffer. For example, some techniques may include pre-computing age matrix entries of an age matrix corresponding to invalid entries of a data buffer based on a validity indication (e.g., a valid bit mask), wherein the validity indication identifies valid entries in the data buffer and the age matrix tracks relative ages of the entries in the data buffer; responsive to data being received for storage in the data buffer, selecting an entry corresponding to an index value in the data buffer from among a set of invalid entries of the data buffer; storing the data in the entry corresponding to the index value; and updating the validity indication to indicate that the entry corresponding to the index value is valid.

公开(公告)号：US12204462B2

公开(公告)日：2025-01-21

申请号：US18132572

申请日：2023-04-10

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F12/14

Abstract: Cache circuitry may be configured to receive a first message to downgrade a permission associated with data stored in a current level cache. For example, the current level cache could be a level two (L2) cache. The cache circuitry could receive the first message from a processor core having a level one (L1) cache. The cache circuitry may forward the first message to a higher level cache. For example, the higher level cache could be a level three (L3) cache. The cache circuitry may downgrade the permission associated with data stored in the current level cache based on receiving a second message from the higher level cache. The cache circuitry may forward the first message before receiving the second message and downgrading the permission. The second message may cause downgrade of the permission in multiple caches (e.g., the L1, L2, and L3 caches).

公开(公告)号：US12189544B2

公开(公告)日：2025-01-07

申请号：US18341093

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F13/16 ,  G06F12/084 ,  G06F13/42

Abstract: First agent circuitry may receive from a second agent a first request and a first set of one or more bits. The first request may be part of a data operation. The first agent circuitry may transmit to the second agent a message including a first response to the first request, the first set of one or more bits, a second request, and a second set of one or more bits. The second set of one or more bits may be generated by the first agent circuitry to transmit state information about the second request. In some implementations, a set of one or more wires may be generated for transmission of the second set of one or more bits. The first agent circuitry may receive from the second agent a second response to the second request and the second set of one or more bits.