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    Common-Mode Impedance Network for Reducing Sensitivity in Oscillators
    31.
    发明申请
    Common-Mode Impedance Network for Reducing Sensitivity in Oscillators 有权

    公开(公告)号：US20170179881A1

    公开(公告)日：2017-06-22

    申请号：US14970865

    申请日：2015-12-16

    Applicant: SILICON LABORATORIES INC.

    Inventor： Aaron J. Caffee

    IPC: H03B5/08

    CPC classification number: H03B5/08 ,  H03B5/12 ,  H03B5/1212 ,  H03B5/1228 ,  H03L1/00 ,  H03L1/026 ,  H03L7/0812

    Abstract: A low-complexity differential inductor and common-mode impedance network for reducing effects of flicker noise in an oscillator output signal have been disclosed. An oscillator includes a planar conductive loop comprising a first terminal, a second terminal, and a center tap. The planar conductive loop is formed from a first conductive layer above an integrated circuit substrate. The center tap is coupled to a first power supply node. The oscillator includes a planar conductive structure extending from a first point proximate to the center tap. The planar conductive structure extends along a line of symmetry of the planar conductive loop to a second point proximate to the first terminal and the second terminal. The planar conductive structure may be formed from the first conductive layer and may be directly coupled to the center tap.

    INTEGRATED CLOCK GENERATOR AND METHOD THEREFOR
    32.
    发明申请
    INTEGRATED CLOCK GENERATOR AND METHOD THEREFOR 有权
    集成时钟发生器及其方法

    公开(公告)号：US20160226443A1

    公开(公告)日：2016-08-04

    申请号：US15096612

    申请日：2016-04-12

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee ,  Brian G. Drost ,  Hendricus de Ruijter

    IPC: H03B5/12 ,  H03L1/00

    CPC classification number: H03B5/1234 ,  H03B5/12 ,  H03B5/1265 ,  H03B5/36 ,  H03L1/00 ,  H03L1/026 ,  H03L7/02 ,  H03L7/087 ,  H03L7/095 ,  H03L7/183 ,  H03L7/1976 ,  H03L7/22 ,  H03L7/23

    Abstract: An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.

    Abstract translation: 集成时钟发生器包括可调谐LC振荡器，可调频率合成器和处理器。 可调LC振荡器具有用于接收振荡器控制信号的输入端和用于提供振荡器时钟信号的输出端。 可调频率合成器具有耦合到可调谐LC振荡器的输出的时钟输入，用于接收合成器控制信号的控制输入和用于提供时钟输出信号的输出。 处理器具有用于接收数据输入信号的输入端，用于提供振荡器控制信号的第一输出端和用于提供合成器控制信号的第二输出端。 处理器提供振荡器控制信号和合成器控制信号，使得可调谐频率合成器以由数据输入信号指示的频率生成输出时钟信号，并且响应于动态条件进一步提供合成器控制信号。

    STRAIN-INSENSITIVE TEMPERATURE SENSOR
    33.
    发明申请
    STRAIN-INSENSITIVE TEMPERATURE SENSOR 审中-公开
    应变敏感温度传感器

    公开(公告)号：US20150285691A1

    公开(公告)日：2015-10-08

    申请号：US14246461

    申请日：2014-04-07

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee ,  Jeffrey L. Sonntag

    IPC: G01K7/24

    CPC classification number: G01K7/24

    Abstract: An apparatus includes a thermistor having a variable resistance with a first dependence on absolute temperature. The apparatus includes a reference resistor having a resistance with a second dependence on absolute temperature, the second dependence being less than or having opposite polarity to the first dependence. The reference resistor includes a switched-capacitor circuit. The apparatus includes a node coupled between the thermistor and the reference resistor. The node is configured to provide a signal indicative of absolute temperature based on the variable resistance and the reference resistance. The signal may be strain-invariant, proportional to a reference voltage, and indicative of a ratio of the variable resistance to the reference resistance. The apparatus may include a feedback circuit configured to maintain the node at a predetermined voltage level.

    Abstract translation: 一种装置包括具有第一依赖于绝对温度的可变电阻的热敏电阻。 该装置包括具有对绝对温度具有第二依赖性的电阻的参考电阻器，第二依赖性小于或具有与第一依赖性相反的极性。 参考电阻器包括开关电容器电路。 该装置包括耦合在热敏电阻和参考电阻之间的节点。 节点被配置为基于可变电阻和参考电阻提供指示绝对温度的信号。 信号可以是应变不变量，与参考电压成比例，并且表示可变电阻与参考电阻的比率。 该装置可以包括被配置为将节点保持在预定电压电平的反馈电路。

    Load compensation to reduce deterministic jitter in clock applications
    34.
    发明授权
    Load compensation to reduce deterministic jitter in clock applications 有权

    公开(公告)号：US10530368B1

    公开(公告)日：2020-01-07

    申请号：US16191755

    申请日：2018-11-15

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee ,  Brian G. Drost

    IPC: H03K23/66 ,  H03K21/02

    Abstract: A clock circuit includes a circuit configured to use a regulated voltage on a regulated voltage node to provide a frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency. The clock circuit includes an auxiliary loading circuit coupled to the regulated voltage node and configured to selectively provide load compensation for a load difference of the circuit. The load difference is a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency. The circuit may include a frequency divider circuit configured to use the regulated voltage on the regulated voltage node to generate the frequency modulated clock signal by frequency dividing an input clock signal according to a divide value vacillating between a first divide value and a second divide value.

    Comb terminals for planar integrated circuit inductor
    35.
    发明授权
    Comb terminals for planar integrated circuit inductor 有权

    公开(公告)号：US10355642B2

    公开(公告)日：2019-07-16

    申请号：US14722607

    申请日：2015-05-27

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee

    IPC: H01F27/28 ,  H01F27/29 ,  H03B5/00 ,  H01F17/00

    Abstract: A technique for reducing series resistance of an inductor system, which may increase the quality factor of the inductor system, has been disclosed. An apparatus includes a conductive loop formed from a first conductive layer. The conductive loop comprises a first terminal and a second terminal. The first terminal includes at least one first conductive finger in the first conductive layer. The second terminal includes at least one second conductive finger in the first conductive layer. The at least one second conductive finger is interdigitated with the at least one first conductive finger without directly contacting the at least one first conductive finger. The apparatus may include a serpentine gap in the first conductive layer. The apparatus may include at least one first conductive via coupled to a second conductive layer and coupled the at least one first conductive fingers, respectively.

    Resistance-to-frequency converter
    37.
    发明授权
    Resistance-to-frequency converter 有权

    公开(公告)号：US09989927B1

    公开(公告)日：2018-06-05

    申请号：US15365869

    申请日：2016-11-30

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee

    IPC: H03M1/50 ,  G04F10/00

    CPC classification number: G04F10/005

    Abstract: A technique for sensing an environmental parameter is disclosed. The technique generates an oscillating signal using a variable resistance sensitive to a variable parameter. A frequency of the oscillating signal is directly dependent on the variable resistance. A time-to-digital converter generates a digital code indicative of the variable resistance. The digital code is generated based on the frequency of the oscillating signal and a second frequency of a reference clock signal. The second frequency is insensitive to the variable parameter. The variable resistance may be a metal resistor and the reference resistance may be generated using a capacitor that is switched at a particular frequency. The measured resistance may be used to control a voltage-controlled oscillator. The oscillating signal frequency may be converted to a digital signal and post-processed for use as an indicator of absolute temperature or other environmental parameter.

    Calibration of transceiver
    39.
    发明授权
    Calibration of transceiver 有权

    公开(公告)号：US09634861B2

    公开(公告)日：2017-04-25

    申请号：US14798545

    申请日：2015-07-14

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee

    IPC: H04L12/423

    CPC classification number: H04L12/423

    Abstract: Techniques for reducing error in time-of-flight measurement due to transceiver latency are disclosed. A method includes determining a first indicator of a first latency of a first transceiver of a first system using a first loopback configuration of the first transceiver. The method includes receiving a second indicator of a second latency of a second transceiver determined by a second system using a second loopback configuration of the second transceiver. The method includes determining a third indicator of a roundtrip latency of a communication from the first transceiver to the second transceiver and back to the first transceiver. The method includes determining a time-of-flight between the first system and the second system based on the first indicator, the second indicator, and the third indicator.

    Oscillator amplifier biasing technique to reduce frequency pulling
    40.
    发明授权
    Oscillator amplifier biasing technique to reduce frequency pulling 有权

    公开(公告)号：US09602110B1

    公开(公告)日：2017-03-21

    申请号：US14963462

    申请日：2015-12-09

    Applicant: Silicon Laboratories Inc.

    Inventor： Aaron J. Caffee

    IPC: H03L1/02

    CPC classification number: H03L1/00 ,  H03L1/026 ,  H03L7/085

    Abstract: An oscillator amplifier biasing technique configures an oscillator amplifier to operate at a bias point causing loading on a tank circuit to have reduced or negligible dependence on amplifier bias conditions or device characteristics. The bias signal level may vary with variation in temperature. The oscillator amplifier biasing technique includes determining a bias signal level that has a minimum sensitivity of the frequency of oscillation as a function of temperature. The technique may store associated data in non-volatile memory to describe the bias signal level dependence on temperature. A digital-to-analog converter may drive the bias signal of the oscillator to the minimum sensitivity point as a function of temperature. The technique may substantially reduce effects of up-conversion of flicker noise in the oscillator output signal as well as improve frequency accuracy in the presence of effects such as mechanical strain and/or aging.

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