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    Dedicated crossbar and barrel shifter block on programmable logic resources
    31.
    发明授权
    Dedicated crossbar and barrel shifter block on programmable logic resources 有权
    专用的横杆和桶形移位器块可编程逻辑资源

    公开(公告)号：US08082526B2

    公开(公告)日：2011-12-20

    申请号：US12069830

    申请日：2008-02-12

    Applicant: Michael Hutton ,  Sinan Kaptanoglu

    Inventor： Michael Hutton ,  Sinan Kaptanoglu

    IPC: G06F17/50

    CPC classification number: H03K19/17736 ,  G06F5/01

    Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

    Abstract translation: 提供专用硬件块用于在可编程逻辑资源中实现十字路口和/或桶形移位器。 横杆和/或桶形移位器电路可以替代可编程逻辑资源上的可编程逻辑区域的一行或多行，一列或多列，一个或多个矩形或其任意组合。 可以通过实施时间复用来进一步改进交叉开关和/或桶形移位器电路的功能。

    Block symmetrization in a field programmable gate array
    33.
    发明授权
    Block symmetrization in a field programmable gate array 有权
    在现场可编程门阵列中的块对称

    公开(公告)号：US07557612B2

    公开(公告)日：2009-07-07

    申请号：US12130876

    申请日：2008-05-30

    Applicant: Sinan Kaptanoglu

    Inventor： Sinan Kaptanoglu

    IPC: H03K19/177

    CPC classification number: H03K19/17736 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17796

    Abstract: An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.

    Abstract translation: FPGA架构具有顶级，中级和低级。 顶级是由I / O块包围的B16x16瓦数组。 中间路由资源是高速公路路由信道，包括互连导体。 在最底层，有块连接路由通道，本地网状路由通道和直接连接互连导体，以将逻辑元件连接到更多的路由资源。 每个B1块包括四组设备。 每个簇包括第一和第二LUT3，LUT2和DFF。 每个LUT3有三个输入和一个输出。 每个LUT2有两个输入和一个输出。 每个DFF都有数据输入和数据输出。 在每个簇中，LUT3的输出被复用到DFF的输入，并且与DFF的输出对称，以形成每个簇的两个输出。

    FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation
    35.
    发明授权
    FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation 有权
    具有两级集群输入互连方案的FPGA架构，无带宽限制

    公开(公告)号：US07408383B1

    公开(公告)日：2008-08-05

    申请号：US11855974

    申请日：2007-09-14

    Applicant: Wenyi Feng ,  Sinan Kaptanoglu

    Inventor： Wenyi Feng ,  Sinan Kaptanoglu

    IPC: H01L25/00 ,  H03K19/177

    CPC classification number: H03K19/17736

    Abstract: An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.

    Abstract translation: 用于可编程逻辑器件的互连架构包括多个互连路由线。 多个第一级复用器的数据输入连接到多个互连路由线，使得每个互连路由线仅连接到一个多路复用器。 多个第二级多路复用器被组织成多路复用器组。 多个查找表中的每一个与多路复用器组中的一个相关联并且具有多个查找表输入。 每个查找表输入耦合到与其相关联的多路复合器组中的一个中的不同的一个二级多路复用器的输出。 第二级复用器的数据输入连接到第一级复用器的输出端，使得每个第一级多路复用器的每个输出端连接到每个复用器组中只有一个二级多路复用器的输入。

    Area efficient fractureable logic elements
    36.
    发明授权
    Area efficient fractureable logic elements 有权
    区域有效的可断裂逻辑元件

    公开(公告)号：US07330052B2

    公开(公告)日：2008-02-12

    申请号：US11234538

    申请日：2005-09-22

    Applicant: Sinan Kaptanoglu ,  Bruce B. Pedersen ,  James G. Schleicher ,  Jinyong Yuan ,  Michael D. Hutton ,  David Lewis

    Inventor： Sinan Kaptanoglu ,  Bruce B. Pedersen ,  James G. Schleicher ,  Jinyong Yuan ,  Michael D. Hutton ,  David Lewis

    IPC: G06F7/38 ,  H03K19/177

    CPC classification number: H03K19/1737

    Abstract: A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTs. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.

    Abstract translation: 可分解逻辑元件包括第一，第二，第三和第四双输入查找表（2-LUT）。 每个2-LUT包括四个存储元件。 每个存储器元件被配置为保持一个数据位。 可分解逻辑元件还包括一组六个输入和被配置为在第一模式和第二模式下操作的控制电路。 当控制电路在第一模式下工作时，使用六个输入和第一，第二，第三和第四2-LUT中的四个产生第一组合输出。 当控制电路在第二模式下操作时，使用六组输入和第一和第二2-LUT组中的三个的第一子集来生成第二组合输出。 另外，当控制电路在第二模式下工作时，使用六组输入和第三和第四2-LUT组中的三个的第二子集来产生第三组合输出，第一和第二子集是不相交的子集 一组六个输入。

    Fracturable lookup table and logic element
    37.
    发明授权
    Fracturable lookup table and logic element 有权
    可破坏的查找表和逻辑元素

    公开(公告)号：US07312632B2

    公开(公告)日：2007-12-25

    申请号：US11753048

    申请日：2007-05-24

    Applicant: David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

    Inventor： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

    IPC: H03K19/173

    CPC classification number: H03K19/17728 ,  H03K19/1737

    Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

    Abstract translation: 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。

    FRACTURABLE LOOKUP TABLE AND LOGIC ELEMENT
    38.
    发明申请
    FRACTURABLE LOOKUP TABLE AND LOGIC ELEMENT 有权
    可折叠的表和逻辑元件

    公开(公告)号：US20070222477A1

    公开(公告)日：2007-09-27

    申请号：US11753048

    申请日：2007-05-24

    Applicant: David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

    Inventor： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

    IPC: H03K19/177

    CPC classification number: H03K19/17728 ,  H03K19/1737

    Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexes with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

    Abstract translation: 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置成包括具有连接到存储器元件的输入的最高级复用的输出和连接到下一个到最高级多路复用器的输出的输出以及具有连接到第二级的多路复用器的输出的第一级多路复用器 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。

    Fracturable incomplete look up table for area efficient logic elements
    39.
    发明授权
    Fracturable incomplete look up table for area efficient logic elements 有权
    用于区域高效逻辑元素的难以置信的不完整查询表

    公开(公告)号：US06888373B2

    公开(公告)日：2005-05-03

    申请号：US10365647

    申请日：2003-02-11

    Applicant: Sinan Kaptanoglu ,  David Lewis ,  Bruce Pedersen

    Inventor： Sinan Kaptanoglu ,  David Lewis ,  Bruce Pedersen

    IPC: H03K19/173 ,  H03K19/177

    CPC classification number: H03K19/17748 ,  H03K19/17728

    Abstract: Disclosed is a configurable logic circuit that includes at least 6 inputs and at least two outputs. The configurable logic element can carry out only a subset of all 6-input logic functions and, thus, requires a substantially smaller silicon area than a 6-LUT that can perform all 6-input logic functions. Also, the configurable logic circuit can be configured such that a first subset of the inputs drive one of the outputs and a second subset of the inputs drive another output.

    Abstract translation: 公开了一种可配置逻辑电路，其包括至少6个输入和至少两个输出。 可配置逻辑元件只能执行所有6输入逻辑功能的一个子集，因此需要比可执行所有6输入逻辑功能的6-LUT更小的硅面积。 而且，可配置逻辑电路可被配置为使得输入的第一子集驱动输出之一，并且输入的第二子集驱动另一输出。

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