Dedicated crossbar and barrel shifter block on programmable logic resources
    2.
    发明授权
    Dedicated crossbar and barrel shifter block on programmable logic resources 有权
    专用的横杆和桶形移位器块可编程逻辑资源

    公开(公告)号:US07355442B1

    公开(公告)日:2008-04-08

    申请号:US11371451

    申请日:2006-03-08

    CPC classification number: H03K19/17736 G06F5/01 G06F7/766 H03K19/17732

    Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

    Abstract translation: 提供专用硬件块用于在可编程逻辑资源中实现十字路口和/或桶形移位器。 横杆和/或桶形移位器电路可以替代可编程逻辑资源上的可编程逻辑区域的一行或多行,一列或多列,一个或多个矩形或其任意组合。 可以通过实施时间复用来进一步改进交叉开关和/或桶形移位器电路的功能。

    Area efficient fractureable logic elements
    3.
    发明申请
    Area efficient fractureable logic elements 有权
    区域有效的可断裂逻辑元件

    公开(公告)号:US20070063732A1

    公开(公告)日:2007-03-22

    申请号:US11234538

    申请日:2005-09-22

    CPC classification number: H03K19/1737

    Abstract: A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTS. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.

    Abstract translation: 可分解逻辑元件包括第一,第二,第三和第四双输入查找表(2-LUT)。 每个2-LUT包括四个存储元件。 每个存储器元件被配置为保持一个数据位。 可分解逻辑元件还包括一组六个输入和被配置为在第一模式和第二模式下操作的控制电路。 当控制电路在第一模式下工作时,使用六个输入和第一,第二,第三和第四2-LUT中的四个产生第一组合输出。 当控制电路在第二模式下操作时,使用该组六个输入和第一和第二2-LUTS中的三个的第一子集来生成第二组合输出。 另外,当控制电路在第二模式下工作时,使用六组输入和第三和第四2-LUT组中的三个的第二子集来产生第三组合输出,第一和第二子集是不相交的子集 一组六个输入。

    Dedicated crossbar and barrel shifter block on programmable logic resources
    4.
    发明授权
    Dedicated crossbar and barrel shifter block on programmable logic resources 有权
    专用的横杆和桶形移位器块可编程逻辑资源

    公开(公告)号:US08082526B2

    公开(公告)日:2011-12-20

    申请号:US12069830

    申请日:2008-02-12

    CPC classification number: H03K19/17736 G06F5/01

    Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

    Abstract translation: 提供专用硬件块用于在可编程逻辑资源中实现十字路口和/或桶形移位器。 横杆和/或桶形移位器电路可以替代可编程逻辑资源上的可编程逻辑区域的一行或多行,一列或多列,一个或多个矩形或其任意组合。 可以通过实施时间复用来进一步改进交叉开关和/或桶形移位器电路的功能。

    Dedicated crossbar and barrel shifter block on programmable logic resources
    6.
    发明授权
    Dedicated crossbar and barrel shifter block on programmable logic resources 失效
    专用的横杆和桶形移位器块可编程逻辑资源

    公开(公告)号:US07042248B1

    公开(公告)日:2006-05-09

    申请号:US10454728

    申请日:2003-06-03

    CPC classification number: H03K19/17736 G06F5/01 G06F7/766 H03K19/17732

    Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

    Abstract translation: 提供专用硬件块用于在可编程逻辑资源中实现十字路口和/或桶形移位器。 横杆和/或桶形移位器电路可以替代可编程逻辑资源上的可编程逻辑区域的一行或多行,一列或多列,一个或多个矩形或其任意组合。 可以通过实施时间复用来进一步改进交叉开关和/或桶形移位器电路的功能。

    (N+1) input flip-flop packing with logic in FPGA architectures
    8.
    发明授权
    (N+1) input flip-flop packing with logic in FPGA architectures 有权
    (N + 1)输入触发器封装,具有FPGA架构中的逻辑

    公开(公告)号:US07944238B2

    公开(公告)日:2011-05-17

    申请号:US12717315

    申请日:2010-03-04

    Inventor: Sinan Kaptanoglu

    CPC classification number: H03K19/1737 H03K19/17728

    Abstract: A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.

    Abstract translation: 逻辑模块和触发器包括具有耦合到路由资源的数据输入的输入多路复用器。 时钟复用器具有耦合到时钟资源的输入和输出。 输入选择多路复用器具有耦合到输入多路复用器的输出的第一输入。 触发器具有耦合到时钟复用器的输出的时钟输入和耦合到输入选择多路复用器的输入的数据输出。 逻辑模块具有耦合到输入选择多路复用器的输出的数据输入。 触发器多路复用器耦合到触发器的数据输入,并具有耦合到第一输入多路复用器的输出,逻辑模块的数据输出和耦合到路由资源的第三输入的输入输入。

    Field programmable gate array architecture having Clos network-based input interconnect
    9.
    发明授权
    Field programmable gate array architecture having Clos network-based input interconnect 有权
    具有基于Clos网络的输入互连的现场可编程门阵列结构

    公开(公告)号:US07924052B1

    公开(公告)日:2011-04-12

    申请号:US12361835

    申请日:2009-01-29

    CPC classification number: H03K19/17736

    Abstract: A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the number of outputs from the first stage.

    Abstract translation: 在具有基于群集的架构的可编程逻辑设备中使用的集群内部路由网络采用基于Clos网络的路由架构。 路由架构是多级阻塞架构,其中第一级的输入数量超过了第一级的输出数量。

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