公开(公告)号：US20050064678A1

公开(公告)日：2005-03-24

申请号：US10945720

申请日：2004-09-20

申请人： Volker Dudek ,  Michael Graf

发明人： Volker Dudek ,  Michael Graf

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： To form a semiconductor component having active regions separated from one another by trenches as isolation structures, a method involves forming a shallow trench in a semiconductor body, thereafter forming a deep trench within the shallow trench in the semiconductor body, and thereafter completely driving dopant atoms into the semiconductor body to form a well region doped with the dopant. The dopant may be previously introduced by implantation into a surface layer, and then the dopant is finally completely driven into the well region by thermally supported diffusion after forming the deep trench. The shallow and deep trenches together form a compound trench with stepped side walls. Two oppositely doped wells may be formed on opposite sides of the compound trench, which thus isolates the two wells from one another. Active regions may be formed in the two wells.

摘要翻译： 为了形成具有通过沟槽作为隔离结构彼此分离的有源区的半导体部件，包括在半导体本体中形成浅沟槽，之后在半导体本体内的浅沟槽内形成深沟槽，然后完全驱动掺杂原子 进入半导体体以形成掺杂有掺杂剂的阱区。 可以预先通过注入掺杂剂到表面层中，然后在形成深沟槽之后通过热支持的扩散将掺杂剂最终完全驱动到阱区中。 浅沟槽和深沟槽一起形成具有阶梯状侧壁的复合沟槽。 可以在复合沟槽的相对侧上形成两个相对掺杂的阱，从而将两个阱彼此隔离。 活性区域可以形成在两个孔中。

公开(公告)号：US20070290226A1

公开(公告)日：2007-12-20

申请号：US11806081

申请日：2007-05-29

申请人： Juergen Berntgen ,  Franz Dietz ,  Michael Graf ,  Stefan Schwantes

发明人： Juergen Berntgen ,  Franz Dietz ,  Michael Graf ,  Stefan Schwantes

IPC分类号： H01L29/74

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L27/0922

摘要： A semiconductor arrangement for an integrated circuit is provided that includes a first region in which a number of components are formed, a second region, a buried insulating layer for vertically insulating the first region, an insulating structure, which is formed between the first region and the second region for laterally insulating the first region from the second region. The insulating structure can have a trench structure with a dielectric and a conductor structure with a semiconductor material. Whereby the trench structure borders on the buried insulating layer, and the conductor structure is designed to conductively connect the first region to the second region.

摘要翻译： 提供一种用于集成电路的半导体装置，其包括其中形成有多个部件的第一区域，第二区域，用于使第一区域垂直绝缘的掩埋绝缘层，形成在第一区域和第二区域之间的绝缘结构 所述第二区域用于使所述第一区域与所述第二区域横向绝缘。 绝缘结构可以具有带电介质的沟槽结构和具有半导体材料的导体结构。 由此沟槽结构与掩埋绝缘层相邻，并且导体结构被设计成将第一区域导电连接到第二区域。

公开(公告)号：US07851326B2

公开(公告)日：2010-12-14

申请号：US11812386

申请日：2007-06-18

申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Thomas Hoffmann

发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Thomas Hoffmann

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler material, a first surface of a semiconductor structure is subjected to a CMP process to level the applied filler material and produce the STI structure; the leveled STI structure thus produced is structured; using the structured, leveled STI structure as a hard mask, at least one deep trench is etched in the area of this STI structure to create the deep trench structures.

摘要翻译： 提供一种用于在半导体衬底的STI结构中制造深沟槽结构的方法，具有以下连续的工艺步骤：在用第一填充材料引入到半导体衬底中的STI凹部的全面填充之后， 对半导体结构进行CMP处理以对施加的填充材料进行平整并产生STI结构; 这样生产的水平STI结构是结构化的; 使用结构化的水平STI结构作为硬掩模，在该STI结构的区域中蚀刻至少一个深沟槽以产生深沟槽结构。

公开(公告)号：US07348256B2

公开(公告)日：2008-03-25

申请号：US11188921

申请日：2005-07-25

申请人： Gayle W. Miller, Jr. ,  Volker Dudek ,  Michael Graf

发明人： Gayle W. Miller, Jr. ,  Volker Dudek ,  Michael Graf

IPC分类号： H01L21/76

CPC分类号： H01L29/7824 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

摘要： A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

摘要翻译： 一种制造电子装置的方法和所得到的电子装置。 该方法包括在绝缘体上硅衬底的最上侧形成栅极氧化物; 在所述栅极氧化物上形成第一多晶硅层; 以及在所述第一多晶硅层上形成第一二氧化硅层。 然后在第一二氧化硅层上形成第一氮化硅层，接着形成第二二氧化硅层。 通过所有以前的介电层蚀刻浅沟槽并进入SOI衬底。 蚀刻的沟槽用另一介质层（例如二氧化硅）填充并平坦化。 去除每个前述电介质层，留下电介质层的最上面的侧壁区域暴露以与稍后施加的多晶硅栅极区域接触。 侧壁区域的形成确保全场氧化物厚度，从而产生具有减小的电场和栅极和漂移区域之间的减小的电容的器件。

公开(公告)号：US20060281291A1

公开(公告)日：2006-12-14

申请号：US11447094

申请日：2006-06-06

申请人： Franz Dietz ,  Volker Dudek ,  Tobias Florian ,  Michael Graf

发明人： Franz Dietz ,  Volker Dudek ,  Tobias Florian ,  Michael Graf

IPC分类号： H01L21/8238 ,  H01L21/44

CPC分类号： H01L21/28537 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L27/095 ,  H01L29/66143 ,  H01L31/108 ,  H01L31/18

摘要： A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal-semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.

摘要翻译： 公开了一种半导体元件中的金属 - 半导体接触的制造方法。 在现有技术方法中金属沉积过程中存在较高的污染风险。 在所公开的方法中，仅在施加保护层系统之后才产生实际的金属 - 半导体或肖特基接触，其结果是可以使用任何金属，特别是铂，而不会有污染的风险。

公开(公告)号：US20050095804A1

公开(公告)日：2005-05-05

申请号：US10946506

申请日：2004-09-20

申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf

发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf

IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L21/20

CPC分类号： H01L29/66659 ,  H01L21/2253 ,  H01L21/26586 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1045 ,  H01L29/7835

摘要： A semiconductor element such as a DMOS-transistor is fabricated in a semiconductor substrate. Wells of opposite conductivity are formed by implanting and then thermally diffusing respective well dopants into preferably spaced-apart areas in the substrate. At least one trench and active regions are formed in the substrate. The trench may be a shallow drift zone trench of a DMOS-transistor, and/or a deep isolation trench. The thermal diffusion of the well dopants includes at least one first diffusion step during a first high temperature drive before forming the trench, and at least one second diffusion step during a second high temperature drive after forming the trench. Dividing the thermal diffusion steps before and after the trench formation achieves an advantageous balance between reducing or avoiding lateral overlapping diffusion of neighboring wells and reducing or avoiding thermally induced defects along the trench boundaries.

摘要翻译： 在半导体衬底中制造诸如DMOS晶体管的半导体元件。 相反电导率的阱通过注入然后将各个掺杂剂热扩散到衬底中优选间隔开的区域中而形成。 在衬底中形成至少一个沟槽和有源区。 沟槽可以是DMOS晶体管的浅漂移区沟槽和/或深隔离沟槽。 阱掺杂剂的热扩散包括在形成沟槽之前的第一高温驱动期间的至少一个第一扩散步骤，以及在形成沟槽之后的第二高温驱动期间的至少一个第二扩散步骤。 在沟槽形成之前和之后划分热扩散步骤在减少或避免相邻阱的横向重叠扩散之间实现有利的平衡，并减少或避免沿着沟槽边界的热诱导缺陷。

公开(公告)号：US20080173940A1

公开(公告)日：2008-07-24

申请号：US12018721

申请日：2008-01-23

申请人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

发明人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

IPC分类号： H01L29/78

CPC分类号： H01L29/7824 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

摘要： A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

摘要翻译： 一种制造电子装置的方法和所得到的电子装置。 该方法包括在绝缘体上硅衬底的最上侧形成栅极氧化物; 在所述栅极氧化物上形成第一多晶硅层; 以及在所述第一多晶硅层上形成第一二氧化硅层。 然后在第一二氧化硅层上形成第一氮化硅层，接着形成第二二氧化硅层。 通过所有以前的介电层蚀刻浅沟槽并进入SOI衬底。 蚀刻的沟槽用另一介质层（例如二氧化硅）填充并平坦化。 去除每个前述电介质层，留下电介质层的最上面的侧壁区域暴露以与稍后施加的多晶硅栅极区域接触。 侧壁区域的形成确保全场氧化物厚度，从而产生具有减小的电场和栅极和漂移区域之间的减小的电容的器件。

公开(公告)号：US07064385B2

公开(公告)日：2006-06-20

申请号：US10946547

申请日：2004-09-20

申请人： Volker Dudek ,  Michael Graf

发明人： Volker Dudek ,  Michael Graf

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

摘要： A DMOS-transistor has a trench bordered by a drift region including two doped wall regions and a doped floor region extending along the walls and the floor of the trench. The laterally extending floor region has a dopant concentration gradient in the lateral direction. For example, the floor region includes at least two differently-doped floor portions successively in the lateral direction. This dopant gradient in the floor region is formed by carrying out at least one dopant implantation from above through the trench using at least one mask to expose a first area while covering a second area of the floor region.

摘要翻译： DMOS晶体管具有由漂移区域界定的沟槽，该漂移区域包括两个掺杂的壁区域和沿沟槽的壁和底部延伸的掺杂的地板区域。 横向延伸的地板区域在横向上具有掺杂剂浓度梯度。 例如，地板区域在横向上连续地包括至少两个不同掺杂的地板部分。 通过使用至少一个掩模通过沟槽从上方进行至少一个掺杂剂注入来形成地板区域中的该掺杂剂梯度，以在覆盖地板区域的第二区域的同时露出第一区域。

公开(公告)号：US20050167779A1

公开(公告)日：2005-08-04

申请号：US11045382

申请日：2005-01-31

申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf

发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/76

CPC分类号： H01L21/84 ,  H01L21/823885 ,  H01L29/7812 ,  H01L29/7824

摘要： Vertically insulated active semiconductor regions having different thicknesses in an SOI wafer, which has an insulating layer, is produced. On the wafer, first active semiconductor regions having a first thickness are arranged in a layer of active semiconductor material. The second active semiconductor regions having a relatively smaller thickness are produced by epitaxial growth proceeding from at least one seed opening in a trench structure. The second semiconductor regions are substantially completely dielectrically insulated, laterally and vertically, from the first semiconductor regions by oxide layers. The width of the seed opening can be defined by lithography.

摘要翻译： 制造具有绝缘层的SOI晶片中具有不同厚度的垂直绝缘的有源半导体区域。 在晶片上，具有第一厚度的第一有源半导体区域被布置在有源半导体材料层中。 具有相对较小厚度的第二有源半导体区域通过从沟槽结构中的至少一个种子开口进行的外延生长产生。 第二半导体区域通过氧化物层从第一半导体区域基本上完全介电绝缘，横向和垂直地绝缘。 种子开口的宽度可以通过光刻来定义。

公开(公告)号：US08378414B2

公开(公告)日：2013-02-19

申请号：US13174398

申请日：2011-06-30

申请人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

发明人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

摘要： By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.

摘要翻译： 通过将晶片的主平面与（100）平面而不是（110）平面对准，可以沿着（100）平面流动的初级电流形成器件。 在这种情况下，设备将在（111）平面上以大约54.7度相交。 这个相交角度可以显着地减少沿（111）方向的应力传播/释放，从而减少缺陷以及泄漏和寄生电流。 泄漏电流降低是短路源极 - 漏极结所需的位错长度变化的直接后果。 通过使用这种技术，对于N沟道CMOS器件，泄漏电流降低高达两个数量级。