公开(公告)号：US20080206931A1

公开(公告)日：2008-08-28

申请号：US12040489

申请日：2008-02-29

申请人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

发明人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

IPC分类号： H01L21/82

CPC分类号： H01L45/1608 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

摘要： A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

摘要翻译： 提出了一种非易失性存储元件和相关联的制造方法和存储元件布置。 非易失性存储元件具有切换材料和存在于切换材料上的第一和第二导电电极。 为了降低成形电压，第一电极具有用于放大由转换材料中的第二电极产生的电场的场强的场放大器结构。 场放大器结构是投影到切换材料中的电极的投影。 存储元件布置具有多个以矩阵形式布置的非易失性存储器元件，并且可以通过以列形式布置的位线和以行形式布置的字线来寻址。

公开(公告)号：US07399673B2

公开(公告)日：2008-07-15

申请号：US11177245

申请日：2005-07-08

申请人： Georg Tempel

发明人： Georg Tempel

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： In a charge-trapping device having an array of memory cells, which are controlled by word lines buried in trenches within a substrate, further trenches are formed parallel to said word lines within said substrate. These subdivide diffusion regions adjacent to the word lines into each a first diffusion region adjacent to a first trench of a first charge-trapping memory cell and a second diffusion region adjacent to a first trench of a second charge-trapping memory cell. The depth of the further trench is sufficient to impede hot charge carrier exchange between neighboring memory cells. For this purpose the further trenches are filled with dielectric material, e.g., an oxide. The depth of the further trenches may be, e.g., half of that of the word line trench, and the width may, e.g., amount to 15-20 nm.

摘要翻译： 在具有由埋在衬底内的沟槽中的字​​线控制的存储单元阵列的电荷俘获装置中，在所述衬底内平行于所述字线形成另外的沟槽。 这些将与字线相邻的扩散区细分成与第一电荷俘获存储单元的第一沟槽相邻的第一扩散区和与第二电荷俘获存储单元的第一沟槽相邻的第二扩散区。 另外的沟槽的深度足以阻止相邻存储器单元之间的热电荷载流子交换。 为此目的，另外的沟槽填充有电介质材料，例如氧化物。 另外的沟槽的深度可以是例如字线沟槽的深度的一半，并且宽度可以例如为15-20nm。

公开(公告)号：US07190022B2

公开(公告)日：2007-03-13

申请号：US11081886

申请日：2005-03-16

申请人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

发明人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

摘要： An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

摘要翻译： 集成电路具有高电压区域，逻辑区域和存储器阵列，用于在包括线性，逻辑和存储器件的芯片上形成系统。 存储器阵列具有布置在三阱结构中的浮置栅极晶体管，其高位漏极位线13基本上与掩埋源极线14垂直对准。 存储器阵列将列可以形成为电荷泵电容器的深沟槽46分离。

公开(公告)号：US07176088B2

公开(公告)日：2007-02-13

申请号：US10513163

申请日：2004-03-18

申请人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

发明人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/66833

摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

摘要翻译： 本发明涉及一种具有表面位线（DLx）和掩埋位线（SLx）的位线结构，埋入位线（SLx）形成在具有沟槽绝缘层（6）的沟槽中，并与掺杂 通过覆盖连接层（12）和沟槽的上部部分区域中的自对准端子层（13）与其接触的区域（10）。

公开(公告)号：US20070007586A1

公开(公告)日：2007-01-11

申请号：US11177245

申请日：2005-07-08

申请人： Georg Tempel

发明人： Georg Tempel

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： In a charge-trapping device having an array of memory cells, which are controlled by word lines buried in trenches within a substrate, further trenches are formed parallel to said word lines within said substrate. These subdivide diffusion regions adjacent to the word lines into each a first diffusion region adjacent to a first trench of a first charge-trapping memory cell and a second diffusion region adjacent to a first trench of a second charge-trapping memory cell. The depth of the further trench is sufficient to impede hot charge carrier exchange between neighboring memory cells. For this purpose the further trenches are filled with dielectric material, e.g., an oxide. The depth of the further trenches may be, e.g., half of that of the word line trench, and the width may, e.g., amount to 15-20 nm.

摘要翻译： 在具有由埋在衬底内的沟槽中的字​​线控制的存储单元阵列的电荷俘获装置中，在所述衬底内平行于所述字线形成另外的沟槽。 这些将与字线相邻的扩散区细分成与第一电荷俘获存储单元的第一沟槽相邻的第一扩散区和与第二电荷俘获存储单元的第一沟槽相邻的第二扩散区。 另外的沟槽的深度足以阻止相邻存储器单元之间的热电荷载流子交换。 为此目的，另外的沟槽填充有电介质材料，例如氧化物。 另外的沟槽的深度可以是例如字线沟槽的深度的一半，并且宽度可以例如为15-20nm。

公开(公告)号：US20050148202A1

公开(公告)日：2005-07-07

申请号：US10987651

申请日：2004-11-12

申请人： Ludger Heiliger ,  Michael Schmidt ,  Georg Tempel

发明人： Ludger Heiliger ,  Michael Schmidt ,  Georg Tempel

IPC分类号： C09J143/04 ,  H01L21/312 ,  H01L21/768 ,  H01L23/532 ,  C09K3/00 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  C09J143/04 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/76831 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A compound and method for sealing or protecting porous materials used in semiconductor fabrication, and in particular for protecting the inner walls of trenches or recesses or vias which are present in such materials. Specifically, compounds and the method of use of the compounds in which polymer compounds comprising functional groups A and B are used to seal surface-exposed pores in porous materials used in chip production.

摘要翻译： 用于半导体制造中用于密封或保护多孔材料的化合物和方法，特别是用于保护存在于这种材料中的沟槽或凹槽或通孔的内壁。 具体地，化合物和使用其中包含官能团A和B的聚合物化合物的化合物的使用方法用于密封用于芯片生产的多孔材料中的表面暴露的孔。

公开(公告)号：US20050116286A1

公开(公告)日：2005-06-02

申请号：US10501430

申请日：2002-12-10

申请人： Franz Schuler ,  Georg Tempel

发明人： Franz Schuler ,  Georg Tempel

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L31/113

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3′) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

摘要翻译： 本发明涉及一种非易失性双晶体管半导体存储单元及相关的制造方法，用于选择晶体管（AT）的源极和漏极区（2）和存储晶体管（ST）形成在衬底（1）中。 存储晶体管（ST）具有第一绝缘层（3），电荷存储层（4），第二绝缘层（5）和存储晶体管控制层（6），而选择晶体管（AT） 绝缘层（3'）和选择晶体管控制层（4 *）。 通过使用不同的材料用于电荷存储层（4）和选择晶体管控制层（4 *），通过使衬底掺杂的电性能保持不变，可以显着提高存储单元的电荷保持性能。

公开(公告)号：US06787843B2

公开(公告)日：2004-09-07

申请号：US10462514

申请日：2003-06-16

申请人： Georg Tempel

发明人： Georg Tempel

IPC分类号： H01L29788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory cell, an associated semiconductor circuit configuration and also a fabrication method, in which, in a substrate, active regions are formed with a first insulating layer situated above them, a charge-storing layer, a second insulating layer and a control layer. In order to realize a particularly small cell area, in a third insulating layer situated thereabove, openings are formed above at least partial regions of source/drain regions, which are each directly contact-connected via the openings by source and drain lines formed on an insulating web.

摘要翻译： 非易失性半导体存储单元，相关半导体电路结构以及制造方法，其中在衬底中形成有位于其上的第一绝缘层的有源区，电荷存储层，第二绝缘层和控制层 层。 为了实现特别小的单元区域，在位于其上的第三绝缘层中，在源极/漏极区域的至少部分区域之上形成开口，所述至少部分区域通过形成在其上的源极和漏极线路经由开口直接接触连接 绝缘网。

公开(公告)号：US06531359B1

公开(公告)日：2003-03-11

申请号：US09596420

申请日：2000-06-19

申请人： Georg Tempel ,  Christoph Kutter

发明人： Georg Tempel ,  Christoph Kutter

IPC分类号： H01L21336

CPC分类号： H01L27/11517

摘要： A method for fabricating a memory cell array, in particular an EPROM or EEPROM memory cell array, includes burying insulation zones on a silicon substrate in accordance with an STI (Shallow Trench Isolation) technique, forming word lines on the insulation zones, covering the word lines with a hard mask and side wall oxides and CVD depositing an oxide or nitride laterally onto the hard mask and onto the side wall oxides to define a spacer. Spacer channels are etched into the insulation zones between adjoining word lines. An SAS (Self Aligned Source) resist mask is applied to mask each two adjacent coated word lines on mutually facing sections, including the spacer channel located between these word lines, while each two adjacent masked word lines of masked word line pairs remain unmasked on mutually facing sections. The SAS resist mask is exposed. Those regions of the insulation zones which are not covered by the SAS perforated mask are anisotropic etched, with a bottom of uncovered spacer channels being lowered down at least to a surface of the uncovered silicon substrate. The SAS perforated mask is removed to uncover a resultant structure.

摘要翻译： 一种用于制造存储单元阵列，特别是EPROM或EEPROM存储单元阵列的方法，包括根据STI（浅沟槽隔离）技术在硅衬底上埋设绝缘区，在绝缘区上形成字线，覆盖字 具有硬掩模和侧壁氧化物的线和CVD将氧化物或氮化物横向沉积到硬掩模上并到侧壁氧化物上以限定间隔物。 间隔通道被蚀刻到相邻字线之间的绝缘区域中。 应用SAS（自对准源）抗蚀剂掩模来掩蔽相互面对的部分上的每两个相邻涂覆的字线，包括位于这些字线之间的间隔通道，而掩蔽的字线对的每两个相邻的被掩蔽的字线保持相互掩蔽 面向部分。 SAS抗蚀剂掩模露出。 未被SAS穿孔掩模覆盖的绝缘区域的那些区域是各向异性蚀刻的，未覆盖的间隔物通道的底部至少下降至未覆盖的硅衬底的表面。 移除SAS穿孔的面罩以露出所得到的结构。

公开(公告)号：US08691660B2

公开(公告)日：2014-04-08

申请号：US12883023

申请日：2010-09-15

申请人： Franz Schuler ,  Georg Tempel

发明人： Franz Schuler ,  Georg Tempel

IPC分类号： H01L21/763

CPC分类号： H01L21/763 ,  H01L21/76229 ,  H01L21/76232

摘要： The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation (STI, TTI) having a deep isolation trench with a covering insulation layer (10, 11), a side wall insulation layer (6) and an electrically conductive filling layer (7), which is electrically connected to a predetermined doping region (1) of the semiconductor substrate in a bottom region of the trench. The use of a trench contact (DTC), which has a deep contact trench with a side wall insulation layer (6) and an electrically conductive filling layer (7), which is likewise electrically connected to the predetermined doping region (1) of the semiconductor substrate in a bottom region of the contact trench, makes it possible to improve the electrical shielding properties with a reduced area requirement.

摘要翻译： 本发明涉及具有沟槽隔离和相关制造方法的半导体部件，具有具有覆盖绝缘层（10,11）的深隔离沟槽的沟槽隔离（STI，TTI），侧壁绝缘层（6）和 导电填充层（7），其在沟槽的底部区域电连接到半导体衬底的预定掺杂区域（1）。 使用与侧壁绝缘层（6）和导电填充层（7）具有深接触沟槽的沟槽接触（DTC），其同样电连接到 半导体衬底在接触沟槽的底部区域中，使得可以以减小的面积要求来改善电屏蔽性能。