公开(公告)号：US20070028029A1

公开(公告)日：2007-02-01

申请号：US11161369

申请日：2005-08-01

申请人： Stephen Morein ,  Robert Bloemer

发明人： Stephen Morein ,  Robert Bloemer

IPC分类号： G06F12/00 ,  G11C7/10

CPC分类号： G06F13/1615 ,  G06F13/1684 ,  G11C7/1072

摘要： A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.

摘要翻译： 一种用于数据传输的方法和装置包括跨越第一双向总线接收第一数据分组并且跨越第二双向总线接收第二数据分组。 接下来，将第一数据分组写入可操作地耦合到第一双向总线和第二双向总线的第一寄存器。 第二数据分组被写入可操作地耦合到第一双向总线和第二双向总线的第二寄存器。 然后，第二数据分组在第一双向总线上传输，并且第一数据分组跨第二个双向总线传输，从而提供跨多个双向总线的数据传输，并提供跨数据传输的数据 要存储在中间寄存器中的总线，以便可以在下一个时钟周期中传输数据，克服任何延迟要求。

公开(公告)号：US20060033735A1

公开(公告)日：2006-02-16

申请号：US10914949

申请日：2004-08-10

申请人： Larry Seiler ,  Laurent Lefebvre ,  Stephen Morein

发明人： Larry Seiler ,  Laurent Lefebvre ,  Stephen Morein

IPC分类号： G06T15/40

CPC分类号： G06T15/40

摘要： A method and apparatus for generating hierarchical depth culling characteristics includes determining a first minimum depth value and a first maximum depth value for a first graphical element. The graphical element may be a primitive. The first minimum depth value may be a minimum Z-plane depth of a pixel within the primitive and a first maximum depth value is a maximum Z-plane value for a pixel within the primitive. The method and apparatus further includes determining a second minimum depth value and a second maximum depth value for a second graphical element, which may be a tile. The method and apparatus further includes calculating an intersection depth range having an intersection minimum depth value and an intersection maximum depth value based on the intersection of the first minimum depth value and the first maximum depth value and the second minimum depth value and the second maximum depth value.

公开(公告)号：US20050210172A1

公开(公告)日：2005-09-22

申请号：US10791519

申请日：2004-03-02

申请人： Andrew Gruber ,  Stephen Morein

发明人： Andrew Gruber ,  Stephen Morein

IPC分类号： G06F3/14 ,  G06F11/00 ,  G06F13/00 ,  G09G5/36

CPC分类号： G06F9/544 ,  G06F3/14 ,  G06F9/542 ,  G09G5/363

摘要： A method and apparatus for processing real time command information includes a real time event engine that monitors event signals. A real time event detector within the real time event engine detects when the real time event occurs. Thereupon, real time event commands within a real time event command buffer are fetched and consumed by the command processor in response to the occurrence of the real time event. The real time event detector contains a plurality of control registers, which contain an event selector register, a real time command buffer point register, and a real time command buffer length register. A driver may program the registers, whereupon a singe real time event detector may be used in conjunction with a plurality of real time event command buffers.

摘要翻译： 用于处理实时命令信息的方法和装置包括监视事件信号的实时事件引擎。 实时事件引擎中的实时事件检测器检测何时发生实时事件。 因此，响应于实时事件的发生，由命令处理器获取并消耗实时事件命令缓冲器内的实时事件命令。 实时事件检测器包含多个控制寄存器，其包含事件选择器寄存器，实时命令缓冲器点寄存器和实时命令缓冲器长度寄存器。 驱动器可以对寄存器进行编程，因此可以结合多个实时事件命令缓冲器使用单个实时事件检测器。

公开(公告)号：US08373709B2

公开(公告)日：2013-02-12

申请号：US12340510

申请日：2008-12-19

申请人： Shahin Solki ,  Stephen Morein ,  Mark S. Grossman

发明人： Shahin Solki ,  Stephen Morein ,  Mark S. Grossman

IPC分类号： G06F15/16

CPC分类号： G06F13/4282 ,  G06F3/14 ,  G06F2213/0026 ,  G06T1/20 ,  G06T1/60 ,  G09G5/006 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/06

摘要： Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

摘要翻译： 本文描述了多处理器架构和方法的实施例。 实施例提供了使用外部桥式集成电路（IC）架构的替代方案。 例如，实施例复用外围总线，使得多个处理器可以使用一个外围接口插槽而不需要外部桥接IC。 实施例可用于已知的总线协议。

公开(公告)号：US08072461B2

公开(公告)日：2011-12-06

申请号：US12718613

申请日：2010-03-05

申请人： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

发明人： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC分类号： G06T1/00 ,  G06F13/18 ,  G06F15/18

CPC分类号： G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

摘要： A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

摘要翻译： 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其基于所述多个像素命令线程和所述多个顶点命令线程的相对优先级从所述多个像素或顶点命令线程中选择命令线程。 所选择的命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。

公开(公告)号：US20100088452A1

公开(公告)日：2010-04-08

申请号：US12245686

申请日：2008-10-03

申请人： Stephen Morein ,  Mark S. Grossman

发明人： Stephen Morein ,  Mark S. Grossman

IPC分类号： G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/4031 ,  G06F13/4068

摘要： An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.

摘要翻译： 描述了内部总线桥结构和方法。 实施例包括具有通过至少一个总线端点内部的主机总线桥耦合到总线根的多个总线端点的系统。 此外，总线端点彼此直接耦合。 实施例可用于已知的总线协议。

公开(公告)号：US20090248941A1

公开(公告)日：2009-10-01

申请号：US12184197

申请日：2008-07-31

申请人： Stephen Morein ,  Mark S. Grossman ,  Warren Fritz Kruger ,  Brian Etscheid

发明人： Stephen Morein ,  Mark S. Grossman ,  Warren Fritz Kruger ,  Brian Etscheid

IPC分类号： G06F13/28 ,  G06F13/20

CPC分类号： G06F13/4265 ,  G06F13/4004 ,  G06F2213/0026

摘要： A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.

摘要翻译： 描述了一种对等专用处理器架构和方法。 实施例包括经由主桥总线耦合到中央处理单元的多个专用处理器，将多个专用处理器中的每一个直接耦合到多个专用处理器中的至少一个的直接总线和耦合到存储器控制器的存储器控​​制器 至多个专用处理器，其中至少一个存储器控制器确定是经由主机总线还是直接总线发送数据，以及是否经由主机总线或直接总线接收数据。

公开(公告)号：US20070222785A1

公开(公告)日：2007-09-27

申请号：US11746427

申请日：2007-05-09

申请人： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

发明人： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC分类号： G06T1/00

CPC分类号： G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

摘要： A graphics processing system comprises a command processing engine capable of processing pixel command threads and vertex command threads. The command processing engine is coupled to both a renderer and a scan converter. Upon completing processing of a command thread, which may comprise a pixel command thread or a vertex command thread, the command engine provides the command thread to either the renderer or the scan converter.

摘要翻译： 图形处理系统包括能够处理像素命令线程和顶点命令线程的命令处理引擎。 命令处理引擎与渲染器和扫描转换器耦合。 在完成可以包括像素命令线程或顶点命令线程的命令线程的处理之后，命令引擎将命令线程提供给渲染器或扫描转换器。

公开(公告)号：US20060033743A1

公开(公告)日：2006-02-16

申请号：US10917268

申请日：2004-08-11

申请人： Stephen Morein

发明人： Stephen Morein

IPC分类号： G06T1/00 ,  G06F15/00

CPC分类号： G06T15/005

摘要： A method for rendering pixels for display includes generating stencil values on a per pixel basis for storage in stencil buffer memory; selecting a group of stencil values that represent a block of pixels; generating compressed stencil data associated with the group of stencil values; and performing stencil testing on a corresponding incoming block of pixels using the compressed stencil data.

公开(公告)号：US20050195188A1

公开(公告)日：2005-09-08

申请号：US10790952

申请日：2004-03-02

申请人： Vineet Goel ,  Stephen Morein ,  R. Hartog

发明人： Vineet Goel ,  Stephen Morein ,  R. Hartog

IPC分类号： G06T15/00 ,  G06T15/30 ,  G06T17/20

CPC分类号： G06T17/20 ,  G06T15/005 ,  G06T2200/28

摘要： A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

摘要翻译： 用于双通道适应性镶嵌的方法和装置包括可操作地耦合以接收原始信息的顶点石斑鱼细分器和索引列表以及耦合到顶点石斑鱼细分器的着色器处理单元。 在第一次通过期间，着色器处理单元接收从原始信息生成的原始索引和多个基元索引中的每一个的自动索引值。 所述方法和装置还包括可操作地耦合到着色器序列的多个顶点着色器输入暂存寄存器，其中多个顶点着色器输入暂存寄存器耦合到多个顶点着色器，使得响应于着色器序列输出，顶点 着色器产生细分因素。 将细分因子提供给顶点分组器细分器，使得顶点分割器细分器在第二遍期间生成每个进程向量输出，每个基元输出和每个分组输出。