公开(公告)号：US07379726B2

公开(公告)日：2008-05-27

申请号：US11779666

申请日：2007-07-18

申请人： Sterling Smith ,  Henry Tin-Hang Yung

发明人： Sterling Smith ,  Henry Tin-Hang Yung

IPC分类号： H04B1/26 ,  G05F3/04

CPC分类号： G06K19/0723 ,  G06K19/0713 ,  G11C5/142 ,  H04B5/0062 ,  H04B7/086 ,  Y02D70/166 ,  Y02D70/42 ,  Y02D70/444

摘要： The present invention provides a passive RFID chip with on-chip charge pumps for generating electrical power for the chip from radio frequencies. The passive RFID chip comprises an analog portion and a digital portion. The analog portion primarily comprises a voltage sensor and an AM data detector. The digital portion comprises a state machine digital logic controller. Incoming RF signals enter the chip via external antennas. The RF signals are converted into regulated DC signals by RF-DC converters with the voltage sensor. The RF-DC converters provide power for all the on-chip components and hence the chip does not require external power supply. The incoming RF signals are demodulated by demodulators and enter the AM data detector where the envelope transitions are detected. A voltage alarm is provided to ensure the voltage level does not drop below an operational level of the chip. The logic signals and programming data are controlled by the state machine digital logic controller and the timing signals are provided by an on-chip oscillator.

摘要翻译： 本发明提供一种具有片上电荷泵的无源RFID芯片，用于从射频产生芯片的电力。 无源RFID芯片包括模拟部分和数字部分。 模拟部分主要包括电压传感器和AM数据检测器。 数字部分包括状态机数字逻辑控制器。 进入的RF信号通过外部天线进入芯片。 RF信号由具有电压传感器的RF-DC转换器转换成稳定的DC信号。 RF-DC转换器为所有片上组件提供电源，因此芯片不需要外部电源。 输入的RF信号由解调器进行解调，并进入检测到包络转换的AM数据检测器。 提供电压报警，以确保电压电平不会下降到芯片的运行水平以下。 逻辑信号和编程数据由状态机数字逻辑控制器控制，定时信号由片上振荡器提供。

公开(公告)号：US07310397B2

公开(公告)日：2007-12-18

申请号：US10698623

申请日：2003-11-03

申请人： Sterling Smith ,  Sheng-Yao Liu ,  Huimin Tsai

发明人： Sterling Smith ,  Sheng-Yao Liu ,  Huimin Tsai

IPC分类号： H04L7/00

CPC分类号： H04L7/0331

摘要： In the data recovery circuit of the invention, a first group of sampling clock pulses is used for sampling approximately the central portions of the data bits in an incoming data stream to produce a first sampled data stream, while a second group of sampling clock pulses is used for sampling approximately the transition portions between every two adjacent data bits in the incoming data stream to produce a second sampled data stream. By detecting the resemblance of each bit in the second sampled data stream to the corresponding two adjacent bits in the first sampled data stream, a phase detection and correction circuit determines an early condition or a late condition for the phases of the sampling clocks and produces a signal to correct the phases of the sampling clocks by shifting the phases backwards or forwards. According to the invention, sampling clocks with lower frequencies can be used for sampling, and the phase error can be corrected to obtain the correct data recovery.

摘要翻译： 在本发明的数据恢复电路中，第一组采样时钟脉冲被用于对输入数据流中的数据位的大部分中心部分采样以产生第一采样数据流，而第二组采样时钟脉冲是 用于对输入数据流中每两个相邻数据位之间的过渡部分进行近似采样，以产生第二采样数据流。 通过检测第二采样数据流中的每一比特相对于第一采样数据流中相应的两个相邻比特，相位检测和校正电路确定采样时钟的相位的早期状态或后期状态，并产生一个 信号通过向后或向后移动相位来校正采样时钟的相位。 根据本发明，可以使用具有较低频率的采样时钟进行采样，并且可以校正相位误差以获得正确的数据恢复。

公开(公告)号：US07274921B2

公开(公告)日：2007-09-25

申请号：US11001133

申请日：2004-12-02

申请人： Sterling Smith ,  Henry Tin-Hang Yung

发明人： Sterling Smith ,  Henry Tin-Hang Yung

IPC分类号： H04B1/26 ,  G05F3/04

CPC分类号： G06K19/0723 ,  G06K19/0713 ,  G11C5/142 ,  H04B5/0062 ,  H04B7/086 ,  Y02D70/166 ,  Y02D70/42 ,  Y02D70/444

摘要： The present invention provides a passive RFID chip with on-chip charge pumps for generating electrical power for the chip from radio frequencies. The passive RFID chip comprises an analog portion and a digital portion. The analog portion primarily comprises a voltage sensor and an AM data detector. The digital portion comprises a state machine digital logic controller. Incoming RF signals enter the chip via external antennas. The RF signals are converted into regulated DC signals by RF-DC converters with the voltage sensor. The RF-DC converters provide power for all the on-chip components and hence the chip does not require external power supply. The incoming RF signals are demodulated by demodulators and enter the AM data detector where the envelope transitions are detected. A voltage alarm is provided to ensure the voltage level does not drop below an operational level of the chip. The logic signals and programming data are controlled by the state machine digital logic controller and the timing signals are provided by an on-chip oscillator.

摘要翻译： 本发明提供一种具有片上电荷泵的无源RFID芯片，用于从射频产生芯片的电力。 无源RFID芯片包括模拟部分和数字部分。 模拟部分主要包括电压传感器和AM数据检测器。 数字部分包括状态机数字逻辑控制器。 进入的RF信号通过外部天线进入芯片。 RF信号由具有电压传感器的RF-DC转换器转换成稳定的DC信号。 RF-DC转换器为所有片上组件提供电源，因此芯片不需要外部电源。 输入的RF信号由解调器进行解调，并进入检测到包络转换的AM数据检测器。 提供电压报警，以确保电压电平不会下降到芯片的运行水平以下。 逻辑信号和编程数据由状态机数字逻辑控制器控制，定时信号由片上振荡器提供。

公开(公告)号：US07026878B2

公开(公告)日：2006-04-11

申请号：US10711175

申请日：2004-08-30

申请人： Sterling Smith

发明人： Sterling Smith

IPC分类号： H03L7/18

CPC分类号： H03L7/1976

摘要： A frequency synthesizer that includes two fractional dividers, two noise-shaped quantizers, three integer dividers, a PLL, an algorithm embodied in control logic, and an adjustment means. The noise-shaped quantizers are used to quantize two fractional (fixed-point) values, derived from the divider control words, into time-varying values. The dividers and PLL are used to generate an output signal by means of multiplying a reference signal by the quotient of the divider control word values. Accordingly, the frequency synthesizer of the present invention can provide a very precise output clock, with the average output frequency being the input frequency multiplied by the quotient of the two divider control words, and with high jitter stability.

摘要翻译： 一种频率合成器，包括两个分数分频器，两个噪声形量化器，三个整数除法器，PLL，控制逻辑中体现的算法，以及调整装置。 噪声量化器用于量化从分频器控制字导出的两个分数（定点）值到时变值。 分频器和PLL用于通过将参考信号乘以分频器控制字值的商来产生输出信号。 因此，本发明的频率合成器可以提供非常精确的输出时钟，平均输出频率是输入频率乘以两个分频器控制字的商，并具有高抖动稳定性。

公开(公告)号：US20050270212A1

公开(公告)日：2005-12-08

申请号：US10908743

申请日：2005-05-24

申请人： Sterling Smith ,  Chia-Ming Yang ,  Chih-Shiun Lu

发明人： Sterling Smith ,  Chia-Ming Yang ,  Chih-Shiun Lu

IPC分类号： H03M1/10 ,  H03M1/12

CPC分类号： H03M1/1028 ,  H03M1/1215

摘要： A high-speed video signal processing system, which includes a reception end for receiving analog signals; a plurality of analog to digital converters coupled to the reception end for converting analog signals received from the reception end to digital signals according to control signals; and an interleaving controller coupled to the plurality of analog to digital converters for generating the control signals to selectively enable the plurality of analog to digital converters according to a predetermined sequence.

摘要翻译： 一种高速视频信号处理系统，包括用于接收模拟信号的接收端; 耦合到接收端的多个模数转换器，用于根据控制信号将从接收端接收的模拟信号转换成数字信号; 以及耦合到所述多个模数转换器的交织控制器，用于产生所述控制信号，以根据预定顺序选择性地启用所述多个模数转换器。

公开(公告)号：US08635569B2

公开(公告)日：2014-01-21

申请号：US12947966

申请日：2010-11-17

申请人： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

发明人： Sterling Smith ,  Hsian-Feng Liu ,  Eer-Wen Tyan ,  Chun-Chia Chen ,  Ming-Chieh Yeh ,  Chung-Ching Chen ,  Yo-Lin Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function.

摘要翻译： 通用存储器I / O生成装置包括定义模块，检索模块，生成模块和布局模块。 定义模块根据多个I / O的引脚配置来定义映射表。 映射表包括多个IO和多个存储器功能之间的对应关系。 检索模块从与多个I / O和多个存储器功能之间的对应关系相关联的候选信息中检索与映射表相对应的控制信息。 生成模块根据控制信息生成硬件描述语言（HDL）文件。 布局模块根据HDL文件对多个I / O进行编程，使得每个I / O可以对应于其相应的存储器功能。

公开(公告)号：US08217815B2

公开(公告)日：2012-07-10

申请号：US12861970

申请日：2010-08-24

申请人： Jianqiu Chen ,  Sterling Smith ,  Jianping Cheng

发明人： Jianqiu Chen ,  Sterling Smith ,  Jianping Cheng

IPC分类号： H03M3/00

CPC分类号： H03M3/474 ,  H03M3/456

摘要： A Sigma-Delta modulator with a shared operational amplifier (op-amp) includes an integrated circuit, having two integrators sharing the op-amp, capable of integrating two input signals of the two integrators; a plurality of quantizers, coupled to the integrating circuit, for comparing outputting signals of the integrators with a predetermined signal and then generating digital outputting signals; a plurality of DACs, respectively coupled to the quantizers, for converting the digital outputting signals to analog feedback signals to the integrators; and a clock generator, for providing clock signals to the integrating circuit and the quantizers. Accordingly, layout area and power consumption of the modulator are reduced due to the shared op-amp.

摘要翻译： 具有共享运算放大器（运算放大器）的Σ-Δ调制器包括集成电路，具有共享运算放大器的两个积分器，能够集成两个积分器的两个输入信号; 多个量化器，耦合到积分电路，用于将积分器的输出信号与预定信号进行比较，然后产生数字输出信号; 分别耦合到量化器的多个DAC，用于将数字输出信号转换为模拟反馈信号到积分器; 以及用于向积分电路和量化器提供时钟信号的时钟发生器。 因此，由于共享运算放大器，调制器的布局面积和功耗降低。

公开(公告)号：US07913907B2

公开(公告)日：2011-03-29

申请号：US11889695

申请日：2007-08-15

申请人： Sterling Smith ,  Chung-Ho Ning

发明人： Sterling Smith ,  Chung-Ho Ning

IPC分类号： G06K7/10

CPC分类号： G06K19/0723 ,  G06K19/0701

摘要： A read state retention circuit and method are disclosed. The read state retention circuit comprises a charge storage unit, charging unit, sensing circuit and state indicator. The charging circuit is coupled to the charge storage unit for charging the charge storage unit. The sensing circuit is coupled to the charge storage unit for sensing a voltage level of the charge storage unit. The state indicator is coupled to the sensing circuit for outputting an indication signal in response to the voltage level.

摘要翻译： 公开了一种读取状态保持电路和方法。 读取状态保持电路包括电荷存储单元，充电单元，感测电路和状态指示器。 充电电路耦合到电荷存储单元以对电荷存储单元进行充电。 感测电路耦合到电荷存储单元，用于感测电荷存储单元的电压电平。 状态指示器耦合到感测电路，用于响应于电压电平输出指示信号。

公开(公告)号：US20110006820A1

公开(公告)日：2011-01-13

申请号：US12825438

申请日：2010-06-29

申请人： Yong-Wang Liu ,  Wen-cai Lu ,  Sterling Smith

发明人： Yong-Wang Liu ,  Wen-cai Lu ,  Sterling Smith

IPC分类号： H03L7/099

CPC分类号： H03L7/1075 ,  H03L7/093 ,  H03L7/0995

摘要： A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, a charge pump, a frequency tuning circuit and an N divider. The frequency tuning circuit includes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the output frequency of the dual PLL circuit to the target frequency; and a current control oscillator (CCO), for generating an output signal of the dual PLL circuit. The output frequency of the output signal is equal to the target frequency.

摘要翻译： 双锁相环（PLL）电路包括相/频检波器，电荷泵，频率调谐电路和N分频器。 频率调谐电路包括：粗调电路，用于粗调双PLL电路的输出频率以近似目标频率; 微调电路，用于将双PLL电路的输出频率微调至目标频率; 以及用于产生双PLL电路的输出信号的电流控制振荡器（CCO）。 输出信号的输出频率等于目标频率。

公开(公告)号：US07702043B2

公开(公告)日：2010-04-20

申请号：US11001121

申请日：2004-12-02

申请人： Sterling Smith ,  Henry Tin-Hang Yung

发明人： Sterling Smith ,  Henry Tin-Hang Yung

IPC分类号： H04L27/06

CPC分类号： G06K19/0723 ,  G06K19/0713 ,  G11C5/142 ,  H04B5/0062 ,  H04B7/086 ,  Y02D70/166 ,  Y02D70/42 ,  Y02D70/444

摘要： The present invention provides a passive RFID chip with on-chip charge pumps for generating electrical power for the chip from radio frequencies. The passive RFID chip comprises an analog portion and a digital portion. The analog portion primarily comprises a voltage sensor and an AM data detector. The digital portion comprises a state machine digital logic controller. Incoming RF signals enter the chip via external antennas. The RF signals are converted into regulated DC signals by RF-DC converters with the voltage sensor. The RF-DC converters provide power for all the on-chip components and hence the chip does not require external power supply. The incoming RF signals are demodulated by demodulators and enter the AM data detector where the envelope transitions are detected. A voltage alarm is provided to ensure the voltage level does not drop below an operational level of the chip. The logic signals and programming data are controlled by the state machine digital logic controller and the timing signals are provided by an on-chip oscillator.

摘要翻译： 本发明提供一种具有片上电荷泵的无源RFID芯片，用于从射频产生芯片的电力。 无源RFID芯片包括模拟部分和数字部分。 模拟部分主要包括电压传感器和AM数据检测器。 数字部分包括状态机数字逻辑控制器。 进入的RF信号通过外部天线进入芯片。 RF信号由具有电压传感器的RF-DC转换器转换成稳定的DC信号。 RF-DC转换器为所有片上组件提供电源，因此芯片不需要外部电源。 输入的RF信号由解调器进行解调，并进入检测到包络转换的AM数据检测器。 提供电压报警，以确保电压电平不会下降到芯片的运行水平以下。 逻辑信号和编程数据由状态机数字逻辑控制器控制，定时信号由片上振荡器提供。