公开(公告)号：US20080159022A1

公开(公告)日：2008-07-03

申请号：US11648855

申请日：2006-12-29

申请人： Suryaprasad Kareenahalli ,  Zohar Bogin

发明人： Suryaprasad Kareenahalli ,  Zohar Bogin

IPC分类号： G11C7/22

CPC分类号： G06F13/4054

摘要： An integrated circuit communicates with memory devices. Data from the memory devices arrives at the integrated circuit with varying propagation delays. The integrated circuit detects the arrival of data from the memory devices, and stores the data in FIFOs. A FIFO drain signal is generated responsive to the detection of the data arrival.

摘要翻译： 集成电路与存储器件通信。 来自存储器件的数据到达具有变化的传播延迟的集成电路。 集成电路检测来自存储器件的数据的到达，并将数据存储在FIFO中。 响应于数据到达的检测而产生FIFO漏极信号。

公开(公告)号：US07350030B2

公开(公告)日：2008-03-25

申请号：US11172401

申请日：2005-06-29

申请人： Hemant G. Rotithor ,  Abhishek Singhal ,  Randy B. Osborne ,  Zohar Bogin ,  Raul N. Gutierrez ,  Buderya S. Acharya ,  Surya Kareenahalli

发明人： Hemant G. Rotithor ,  Abhishek Singhal ,  Randy B. Osborne ,  Zohar Bogin ,  Raul N. Gutierrez ,  Buderya S. Acharya ,  Surya Kareenahalli

IPC分类号： G06F12/00 ,  G06F9/00

CPC分类号： G06F12/0862 ,  G06F12/0215 ,  G06F12/0607 ,  G06F2212/6022 ,  G06F2212/6026

摘要： The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

摘要翻译： 本发明包括一种从具有交织信道的存储装置预取的装置和方法。 芯片组预取器包括用于检测流中的步幅的步幅检测器，用于将预取插入存储器件的预取注入器，用于将预取映射到存储器件的每个通道的通道映射器，调度器以将预取计划到存储器上 DRAM状态感知方式的设备，限制预取数量的限制启发式，以及预取数据缓冲器来存储预取数据。 预取方法包括跟踪流的状态，检测一条流上的步幅，选择用于预取注入的步幅的流，从所选择的流中引入预取，将预取映射到每个交错通道，注入预取 从所选择的流到每个交织的信道，并且以DRAM状态感知的方式将预取调度到存储器设备上。

公开(公告)号：US20070073977A1

公开(公告)日：2007-03-29

申请号：US11241363

申请日：2005-09-29

申请人： Robert Safranek ,  Robert Greiner ,  David Hill ,  Buderya Acharya ,  Zohar Bogin ,  Derek Bachand ,  Robert Beers

发明人： Robert Safranek ,  Robert Greiner ,  David Hill ,  Buderya Acharya ,  Zohar Bogin ,  Derek Bachand ,  Robert Beers

IPC分类号： G06F13/28

CPC分类号： G06F12/0835

摘要： In one embodiment, the present invention includes a method for performing an operation in a processor of a uniprocessor system, initiating a write transaction to send a result of the operation to a memory of the uniprocessor system, and issuing a global observation point for the write transaction to the processor before the result is written into the memory. In some embodiments, the global observation point may be issued earlier than if the processor were in a multiprocessor system. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于在单处理器系统的处理器中执行操作的方法，发起写入事务以将操作结果发送到单处理器系统的存储器，以及发出用于写入的全局观察点 事务处理器之前，将结果写入内存。 在一些实施例中，全局观测点可以比处理器处于多处理器系统中的情况更早发布。 描述和要求保护其他实施例。

公开(公告)号：US07093115B2

公开(公告)日：2006-08-15

申请号：US10326394

申请日：2002-12-19

申请人： David I. Poisner ,  Michael N. Derr ,  Darren Abramson ,  Zohar Bogin ,  Adit Tarmaster ,  William Knolla

发明人： David I. Poisner ,  Michael N. Derr ,  Darren Abramson ,  Zohar Bogin ,  Adit Tarmaster ,  William Knolla

IPC分类号： G06F15/177 ,  G06F11/22

CPC分类号： G06F9/4403

摘要： Embodiments of the present invention provide a method and apparatus for detecting an interruption in memory initialization. A status bit for indicating whether memory initialization was interrupted or not is stored in a register. A basic input/output system (BIOS) sets the status bit prior to initialization and clears the status bit after initialization. The status bit cannot be reset by a standard platform reset. In operation, as the system is reset or turned on and prior to initialization, the BIOS checks the status bit to detect possible improper memory initialization. When the status bit is set, the BIOS concludes that a memory initialization had not completed and thus might be incorrect. The BIOS then causes power to be cycled to memory and any other steps needed are taken to return the memory to a functional state.

摘要翻译： 本发明的实施例提供了一种用于检测存储器初始化中的中断的方法和装置。 用于指示存储器初始化是否中断的状态位是否存储在寄存器中。 基本输入/输出系统（BIOS）在初始化之前设置状态位，并在初始化后清除状态位。 状态位不能通过标准平台复位来复位。 在操作中，当系统复位或打开和初始化之前，BIOS检查状态位以检测可能的不正确的存储器初始化。 当状态位置位时，BIOS得出结论：存储器初始化尚未完成，因此可能不正确。 BIOS然后使电源循环到存储器，并且采取任何其他步骤来将存储器返回到功能状态。

公开(公告)号：US07009894B2

公开(公告)日：2006-03-07

申请号：US10784047

申请日：2004-02-19

申请人： Anoop Mukker ,  Zohar Bogin ,  Dave Freker ,  Navneet Dour

发明人： Anoop Mukker ,  Zohar Bogin ,  Dave Freker ,  Navneet Dour

IPC分类号： G11C7/00

CPC分类号： G11C7/1048

摘要： A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memory, deactivating the termination loads. The method also involves, for a second read of information from the memory, activating the termination loads.

摘要翻译： 描述了一种方法，其涉及对来自存储器的信息的第一次读取，激活存储器控制器和存储器之间的数据总线的存储器控​​制器侧的终止负载。 该方法还涉及为了将信息写入存储器，停用终止负载。 该方法还涉及对来自存储器的信息的第二次读取，激活终止负载。

公开(公告)号：US20050185480A1

公开(公告)日：2005-08-25

申请号：US10784047

申请日：2004-02-19

申请人： Anoop Mukker ,  Zohar Bogin ,  Dave Freker ,  Navneet Dour

发明人： Anoop Mukker ,  Zohar Bogin ,  Dave Freker ,  Navneet Dour

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1048

摘要： A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memory, deactivating the termination loads. The method also involves, for a second read of information from the memory, activating the termination loads.

摘要翻译： 描述了一种方法，其涉及对来自存储器的信息的第一次读取，激活存储器控制器和存储器之间的数据总线的存储器控​​制器侧的终止负载。 该方法还涉及为了将信息写入存储器，停用终止负载。 该方法还涉及对来自存储器的信息的第二次读取，激活终止负载。

公开(公告)号：US20050114564A1

公开(公告)日：2005-05-26

申请号：US10723135

申请日：2003-11-25

申请人： Zohar Bogin ,  Brent Chartrand ,  Arthur Hunter ,  Mihir Shah

发明人： Zohar Bogin ,  Brent Chartrand ,  Arthur Hunter ,  Mihir Shah

IPC分类号： G06F3/16 ,  G10L19/00 ,  G11B20/10 ,  G06F13/00

CPC分类号： G06F3/16 ,  G10L19/0018

摘要： Machine-readable media, methods, and apparatus are described to recover from stream under-run and/or over-run conditions. In some embodiments, an audio controller may discard any partial sample block of the stream.

摘要翻译： 描述了机器可读介质，方法和装置，以从流下运行和/或超载条件中恢复。 在一些实施例中，音频控制器可以丢弃流的任何部分采样块。

公开(公告)号：US20050091481A1

公开(公告)日：2005-04-28

申请号：US10693226

申请日：2003-10-24

申请人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

发明人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

IPC分类号： G06F1/24 ,  G06F15/177

CPC分类号： G06F1/24

摘要： A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.

摘要翻译： 已经公开了响应于系统热复位来确定地关闭存储器件的方法。 该方法的一个实施例包括在系统中响应于系统中的第二类型的复位而引起系统中的多个存储器件中的第一类型的复位，如果存储器件未被初始化并且使能存储器中的确定性关断模式 控制器，其在存储器件初始化之后耦合到存储器件。 描述和要求保护其他实施例。

公开(公告)号：US06784890B1

公开(公告)日：2004-08-31

申请号：US09033529

申请日：1998-03-02

申请人： Brian L. Bergeson ,  Zohar Bogin ,  Vincent E. VonBokern

发明人： Brian L. Bergeson ,  Zohar Bogin ,  Vincent E. VonBokern

IPC分类号： G06F1318

CPC分类号： G06F13/1642

摘要： A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles processing non-expedite requests during the monitoring window.

摘要翻译： 一种用于控制加速循环的方法，其具有确定用于在预定监视窗口期间对组件进行的数据传送请求的时钟周期数量的步骤，并且确保在监视窗口期间处理非加速请求的最小数量的时钟周期。

公开(公告)号：US06499085B2

公开(公告)日：2002-12-24

申请号：US09752846

申请日：2000-12-29

申请人： Zohar Bogin ,  David J. Harriman ,  Zdzislaw A. Wirkus ,  Satish Acharya

发明人： Zohar Bogin ,  David J. Harriman ,  Zdzislaw A. Wirkus ,  Satish Acharya

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F12/0835

摘要： A system is described for servicing a full cache line in response to a partial cache line request. The system includes a storage to store at least one cache line, a hit/miss detector, and a data mover. The hit/miss detector receives a partial cache line read request from a requesting agent and dispatches a fetch request to a memory device to fetch a full cache line data that contains data requested in the partial cache line read request from the requesting agent. The data mover loads the storage with the full cache line data returned from the memory device and forwards a portion of the full cache line data requested by the requesting agent. If data specified in a subsequent partial cache line request from the requesting agent is contained within the full cache line data specified in the previously dispatched fetch request, the hit/miss detector will send a command to the data mover to forward another portion of the full cache line data stored in the storage to the requesting agent. In one embodiment, the system also includes a write combining logic to combine two or more consecutive write requests that meet defined conditions into a single write request.