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公开(公告)号：US06784890B1
公开(公告)日：2004-08-31
申请号：US09033529
申请日：1998-03-02
IPC分类号： G06F1318
CPC分类号： G06F13/1642
摘要： A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles processing non-expedite requests during the monitoring window.
摘要翻译： 一种用于控制加速循环的方法，其具有确定用于在预定监视窗口期间对组件进行的数据传送请求的时钟周期数量的步骤，并且确保在监视窗口期间处理非加速请求的最小数量的时钟周期。
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公开(公告)号：US06470238B1
公开(公告)日：2002-10-22
申请号：US09335101
申请日：1999-06-17
申请人： Puthiya K. Nizar , David J. McDonnell , Brian K. Langendorf , Michael G. LaTondre , Jeff L. Rabe , Tom A. Sutera , Zohar Bogin , Vincent E. VonBokern
发明人： Puthiya K. Nizar , David J. McDonnell , Brian K. Langendorf , Michael G. LaTondre , Jeff L. Rabe , Tom A. Sutera , Zohar Bogin , Vincent E. VonBokern
IPC分类号： G05D2300
CPC分类号： G06F13/1668
摘要： A method for controlling device temperature. The method involves determining access rate to a component, comparing the access rate with a predetermined threshold modified by a weighted value and controlling the temperature of the component through corrective action.
摘要翻译： 一种控制装置温度的方法。 该方法涉及确定对组件的访问速率，将访问速率与由加权值修改的预定阈值进行比较，并通过纠正措施控制组件的温度。
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公开(公告)号：US5953685A
公开(公告)日：1999-09-14
申请号：US979835
申请日：1997-11-26
申请人： Zohar Bogin , Vincent E. VonBokern
发明人： Zohar Bogin , Vincent E. VonBokern
摘要： A method for controlling core logic temperature. The core logic having a memory controller and memory components coupled to system memory. The method having the step of determining access rate to the system memory through the core logic and controlling the temperature of the core logic by adjusting the access rate.
摘要翻译： 一种控制核心逻辑温度的方法。 核心逻辑具有存储器控制器和耦合到系统存储器的存储器组件。 该方法具有通过核心逻辑确定对系统存储器的访问速率并通过调整访问速率来控制核心逻辑的温度的步骤。
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公开(公告)号：US06173217B2
公开(公告)日：2001-01-09
申请号：US08990711
申请日：1997-12-15
申请人： Zohar Bogin , Vincent E. VonBokern
发明人： Zohar Bogin , Vincent E. VonBokern
IPC分类号： G05D2300
摘要： A method for controlling core logic temperature. The core logic having a memory controller and memory components coupled to system memory. The method having the step of determining access rate to the system memory through the core logic and controlling the temperature of the core logic by adjusting the access rate.
摘要翻译： 一种控制核心逻辑温度的方法。 核心逻辑具有存储器控制器和耦合到系统存储器的存储器组件。 该方法具有通过核心逻辑确定对系统存储器的访问速率并通过调整访问速率来控制核心逻辑的温度的步骤。
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公开(公告)号：US06314472B1
公开(公告)日：2001-11-06
申请号：US09203127
申请日：1998-12-01
IPC分类号： G06F300
CPC分类号： G06F13/161
摘要： A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.
摘要翻译： 提供计算机系统。 计算机系统包括主机处理器（HP），系统存储器（SM）以及输入/输出（I / O）主设备，以执行对SM的连续数据流的读取。 计算机系统还包括耦合到HP，SM和I / O主设备的桥。 当I / O主设备从SM读取连续的数据流时，桥接器向前读取SM。 响应于I / O主设备的脱离接口，桥接器在对SM进行访问提交之前中止对SM的预读访问。
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6.发明授权Apparatus and method for preventing access to SMRAM space through AGP addressing 失效通过AGP寻址防止访问SMRAM空间的装置和方法公开(公告)号：US06192455B1
公开(公告)日：2001-02-20
申请号：US09050627
申请日：1998-03-30
申请人： Zohar Bogin , Vincent E. VonBokern
发明人： Zohar Bogin , Vincent E. VonBokern
IPC分类号： G06F1200
CPC分类号： G06F12/1036 , G06F12/1441
摘要： A method for preventing access to a system management random access memory (SMRAM) space is disclosed. The method intercepts access to an accelerated graphics port (AGP) aperture memory space and re-directs the access to non-SMRAM space if the access is directed to the SMRAM space.
摘要翻译： 公开了一种防止访问系统管理随机存取存储器（SMRAM）空间的方法。 该方法拦截对加速图形端口（AGP）光圈存储器空间的访问，并且如果访问指向SMRAM空间，则重新引导对非SMRAM空间的访问。
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公开(公告)号：US6157397A
公开(公告)日：2000-12-05
申请号：US50381
申请日：1998-03-30
CPC分类号： G06F3/14
摘要： A method for graphics device read and processor write coherency receives a write request from a processor to write data to a storage element for a component to read and flushes the data to the storage element prior to the component reading the address associated with the data in the storage element.
摘要翻译： 用于图形设备读取和处理器写入一致性的方法从处理器接收写入请求，以将数据写入存储元件，以便组件在组件读取与数据相关联的地址之前将数据读取和刷新到存储元件 存储元件
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公开(公告)号：US20080133952A1
公开(公告)日：2008-06-05
申请号：US11633183
申请日：2006-12-04
申请人： Chai Huat Gan , Darren Abramson , Zohar Bogin
发明人： Chai Huat Gan , Darren Abramson , Zohar Bogin
CPC分类号： G06F1/3225
摘要： For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.
摘要翻译： 对于由计算机系统处理的等时数据流，例如高清晰度音频流，实施例跟踪用于数据流的输入和输出缓冲器中的可用空间。 缓冲器中的可用空间确定是否满足各种低功率进入和退出阈值。 如果满足所有低功率入口阈值，则诸如时钟，锁相环和直接介质接口链路的各种电路可能被置于低功率状态，并且数据流控制器进入空闲窗口，使得存储器请求不是 服务。 在此期间，系统DRAM可能会开始刷新。 一旦输入低功率状态，如果满足任何退出阈值，则低功率状态结束。 描述和要求保护其他实施例。
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9.发明授权公开(公告)号：US07181605B2
公开(公告)日：2007-02-20
申请号：US10693226
申请日：2003-10-24
申请人： Zohar Bogin , Surya Kareenahalli , Anoop Mukker , David Sastry , Tuong Trieu
发明人： Zohar Bogin , Surya Kareenahalli , Anoop Mukker , David Sastry , Tuong Trieu
IPC分类号： G06F9/00
CPC分类号： G06F1/24
摘要： A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.
摘要翻译： 已经公开了响应于系统热复位来确定地关闭存储器件的方法。 该方法的一个实施例包括在系统中响应于系统中的第二类型的复位而引起系统中的多个存储器件中的第一类型的复位，如果存储器件未被初始化并且使能存储器中的确定性关断模式 控制器，其在存储器件初始化之后耦合到存储器件。 描述和要求保护其他实施例。
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公开(公告)号：US07082480B2
公开(公告)日：2006-07-25
申请号：US10674944
申请日：2003-09-29
申请人： Zohar Bogin , Serafin E. Garcia
发明人： Zohar Bogin , Serafin E. Garcia
IPC分类号： G06F3/00
CPC分类号： G06F13/24 , G06F13/385
摘要： A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.
摘要翻译： 在具有调度器和多个下行命令队列的计算机系统中防止死锁和活动锁的技术的组合。 在一个实施例中，需要在所有受影响的下游命令队列中同时可用空间的广播事务变成延迟的事务，使得命令队列被保留，并且重试其他事务直到广播事务完成。 在另一个实施例中，如果事务在预定时间内未完成，则使用拯救计时器推迟事务。 在另一个实施例中，如果存在小于可用于该事务的预定量的下游缓冲区空间，则潜在地解决由可编程属性映射控制的存储空间的锁定事务被处理为延迟事务。
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