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21 条记录 (耗时 0.028 秒)

    Dynamically activated memory controller data termination
    1.
    发明授权
    Dynamically activated memory controller data termination 有权
    动态激活内存控制器数据终止

    公开(公告)号：US07009894B2

    公开(公告)日：2006-03-07

    申请号：US10784047

    申请日：2004-02-19

    申请人： Anoop Mukker ,  Zohar Bogin ,  Dave Freker ,  Navneet Dour

    发明人： Anoop Mukker ,  Zohar Bogin ,  Dave Freker ,  Navneet Dour

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1048

    摘要： A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memory, deactivating the termination loads. The method also involves, for a second read of information from the memory, activating the termination loads.

    摘要翻译： 描述了一种方法，其涉及对来自存储器的信息的第一次读取，激活存储器控制器和存储器之间的数据总线的存储器控​​制器侧的终止负载。 该方法还涉及为了将信息写入存储器，停用终止负载。 该方法还涉及对来自存储器的信息的第二次读取，激活终止负载。

    DYNAMICALLY ACTIVATED MEMORY CONTROLLER DATA TERMINATION
    2.
    发明申请
    DYNAMICALLY ACTIVATED MEMORY CONTROLLER DATA TERMINATION 有权
    动态记忆控制器动态数据终止

    公开(公告)号：US20050185480A1

    公开(公告)日：2005-08-25

    申请号：US10784047

    申请日：2004-02-19

    申请人： Anoop Mukker ,  Zohar Bogin ,  Dave Freker ,  Navneet Dour

    发明人： Anoop Mukker ,  Zohar Bogin ,  Dave Freker ,  Navneet Dour

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/1048

    摘要： A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memory, deactivating the termination loads. The method also involves, for a second read of information from the memory, activating the termination loads.

    摘要翻译： 描述了一种方法，其涉及对来自存储器的信息的第一次读取，激活存储器控制器和存储器之间的数据总线的存储器控​​制器侧的终止负载。 该方法还涉及为了将信息写入存储器，停用终止负载。 该方法还涉及对来自存储器的信息的第二次读取，激活终止负载。

    Deterministic shut down of memory devices in response to a system warm reset
    4.
    发明授权
    Deterministic shut down of memory devices in response to a system warm reset 有权
    响应于系统热复位，确定性地关闭存储器件

    公开(公告)号：US07181605B2

    公开(公告)日：2007-02-20

    申请号：US10693226

    申请日：2003-10-24

    申请人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

    发明人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

    IPC分类号： G06F9/00

    CPC分类号： G06F1/24

    摘要： A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.

    摘要翻译： 已经公开了响应于系统热复位来确定地关闭存储器件的方法。 该方法的一个实施例包括在系统中响应于系统中的第二类型的复位而引起系统中的多个存储器件中的第一类型的复位，如果存储器件未被初始化并且使能存储器中的确定性关断模式 控制器，其在存储器件初始化之后耦合到存储器件。 描述和要求保护其他实施例。

    Deterministic shut down of memory devices in response to a system warm reset
    6.
    发明申请
    Deterministic shut down of memory devices in response to a system warm reset 有权
    响应于系统热复位，确定性地关闭存储器件

    公开(公告)号：US20050091481A1

    公开(公告)日：2005-04-28

    申请号：US10693226

    申请日：2003-10-24

    申请人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

    发明人： Zohar Bogin ,  Surya Kareenahalli ,  Anoop Mukker ,  David Sastry ,  Tuong Trieu

    IPC分类号： G06F1/24 ,  G06F15/177

    CPC分类号： G06F1/24

    摘要： A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.

    摘要翻译： 已经公开了响应于系统热复位来确定地关闭存储器件的方法。 该方法的一个实施例包括在系统中响应于系统中的第二类型的复位而引起系统中的多个存储器件中的第一类型的复位，如果存储器件未被初始化并且使能存储器中的确定性关断模式 控制器，其在存储器件初始化之后耦合到存储器件。 描述和要求保护其他实施例。

    Apparatus and a method to adjust signal timing on a memory interface
    8.
    发明申请
    Apparatus and a method to adjust signal timing on a memory interface 审中-公开
    用于调整存储器接口上的信号定时的装置和方法

    公开(公告)号：US20050190193A1

    公开(公告)日：2005-09-01

    申请号：US10791180

    申请日：2004-03-01

    申请人： David Freker ,  Zohar Bogin ,  Dour Navneet ,  Anoop Mukker ,  Tuong Trieu

    发明人： David Freker ,  Zohar Bogin ,  Dour Navneet ,  Anoop Mukker ,  Tuong Trieu

    IPC分类号： G06F13/00 ,  G06F13/16 ,  G06F13/372

    CPC分类号： G06F13/1689

    摘要： An apparatus and a method for adjusting signal timing in a memory interface have been disclosed. One embodiment of the apparatus includes a number of slave delay lock loops (DLLs) in a memory interface to adjust timing between a number of signals to compensate for timing skew, and a number of input/output (I/O) buffers to output the adjusted signals to one or more memory devices coupled to the memory interface. Other embodiments are described and claimed.

    摘要翻译： 已经公开了一种用于调整存储器接口中的信号定时的装置和方法。 该装置的一个实施例包括在存储器接口中的多个从属延迟锁定环（DLL），用于调整多个信号之间的定时以补偿定时偏差，以及多个输入/输出（I / O）缓冲器，以输出 调整的信号到耦合到存储器接口的一个或多个存储器件。 描述和要求保护其他实施例。

    Hardware detected command-per-clock
    10.
    发明申请
    Hardware detected command-per-clock 失效
    硬件检测每个时钟指令

    公开(公告)号：US20050144374A1

    公开(公告)日：2005-06-30

    申请号：US10749183

    申请日：2003-12-30

    申请人： Suryaprasad Karecnahalli ,  Zohar Bogin ,  Anoop Mukker

    发明人： Suryaprasad Karecnahalli ,  Zohar Bogin ,  Anoop Mukker

    IPC分类号： G06F12/00 ,  G06F13/16

    CPC分类号： G06F13/1631

    摘要： A memory controller is coupled to a memory device via a memory channel. The memory controller includes a command-per-clock detection unit that compares a portion of a current address with a portion of a previous address. If there is a match, then the memory controller can continue to assert a chip select line coupled to the memory device. The command-per-clock detection unit checks to see whether only certain low-order bits of the address lines are toggling between the current and previous addresses. Additional copies of address lines for particular low-order bits are provided to the memory device to reduce loading on the low order bit address lines, allowing the low order bit address lines to toggle quickly in order to avoid the necessity of inserting a one clock period wait state. If the command-per-clock detection unit does not find a match (meaning that more than the low order address bits are toggling) then the wait state is inserted by deasserting the chip select line for a clock period.

    摘要翻译： 存储器控制器经由存储器通道耦合到存储器件。 存储器控制器包括每时钟脉冲检测单元，其将当前地址的一部分与先前地址的一部分进行比较。 如果存在匹配，则存储器控制器可以继续断言耦合到存储器件的芯片选择线。 命令/时钟检测单元检查地址线的某些低位是否在当前地址和以前的地址之间切换。 用于特定低位的地址线的附加副本被提供给存储器件以减少低位位地址线上的负载，允许低位位地址线快速切换，以避免插入一个时钟周期 等待状态 如果命令/时钟检测单元没有找到匹配（意味着比低位地址位多于切换），则通过在芯片选择线上断开时钟周期来插入等待状态。