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    Forming integrated inductors and transformers with embedded magnetic cores
    32.
    发明授权
    Forming integrated inductors and transformers with embedded magnetic cores 有权

    公开(公告)号：US12057264B2

    公开(公告)日：2024-08-06

    申请号：US15787451

    申请日：2017-10-18

    Applicant: Texas Instruments Incorporated

    Inventor： Anindya Poddar

    IPC: H01F41/04

    CPC classification number: H01F41/046 ,  Y10T29/49073

    Abstract: In accordance with an embodiment of the application a method of forming an integrated magnetic device is described. A prepreg or core is mounted on a carrier. A winding layer is plated and patterned on the prepreg or core. Vias are plated. The silicon is placed on a die attach pad, ensuring sufficient clearance of die to vias and d/a char. The assembly is laminated and grinded to expose the vias. A 2nd layer of vias is provided by sputtering or plating followed by laminating assembly; and grinding assembly to expose vias. The windings are plated and patterned. A solder mask (SMSK) is applied and assembly finished.

    PACKAGE FOR STRESS SENSITIVE COMPONENT AND SEMICONDUCTOR DEVICE
    34.
    发明申请
    PACKAGE FOR STRESS SENSITIVE COMPONENT AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230005881A1

    公开(公告)日：2023-01-05

    申请号：US17364769

    申请日：2021-06-30

    Applicant: Texas Instruments Incorporated

    Inventor： Anindya Poddar ,  Mahmud Chowdhury ,  Hau Nguyen ,  Masamitsu Matsuura ,  Ting-Ta Yen

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

    Abstract: In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.

    FLIP CHIP PACKAGED DEVICES WITH THERMAL PAD
    35.
    发明申请
    FLIP CHIP PACKAGED DEVICES WITH THERMAL PAD 有权

    公开(公告)号：US20230005880A1

    公开(公告)日：2023-01-05

    申请号：US17364735

    申请日：2021-06-30

    Applicant: Texas Instruments Incorporated

    Inventor： Anindya Poddar ,  Ashok Surendra Prabhu ,  Hau Nguyen ,  Kurt Edward Sincerbox ,  Makoto Shibuya

    IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48

    Abstract: In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.

    SEMICONDUCTOR PACKAGE WITH ISOLATED HEAT SPREADER
    36.
    发明申请
    SEMICONDUCTOR PACKAGE WITH ISOLATED HEAT SPREADER 有权

    公开(公告)号：US20220238424A1

    公开(公告)日：2022-07-28

    申请号：US17719246

    申请日：2022-04-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Anindya Poddar ,  Woochan Kim ,  Vivek Kishorechand Arora

    IPC: H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

    Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

    Embedded die packaging with integrated ceramic substrate
    38.
    发明授权
    Embedded die packaging with integrated ceramic substrate 有权

    公开(公告)号：US11183460B2

    公开(公告)日：2021-11-23

    申请号：US16132906

    申请日：2018-09-17

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/538 ,  H01L23/373 ,  H01L21/56 ,  H01L23/498

    Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

    PACKAGED SEMICONDUCTOR DEVICES FOR HIGH VOLTAGE WITH DIE EDGE PROTECTION
    39.
    发明申请
    PACKAGED SEMICONDUCTOR DEVICES FOR HIGH VOLTAGE WITH DIE EDGE PROTECTION 审中-公开

    公开(公告)号：US20200381322A1

    公开(公告)日：2020-12-03

    申请号：US16996742

    申请日：2020-08-18

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Vivek Aurora ,  Anindya Poddar

    IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

    Abstract: In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

    Packaged semiconductor devices for high voltage with die edge protection
    40.
    发明授权
    Packaged semiconductor devices for high voltage with die edge protection 有权

    公开(公告)号：US10748827B2

    公开(公告)日：2020-08-18

    申请号：US16120922

    申请日：2018-09-04

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Vivek Arora ,  Anindya Poddar

    IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/56

    Abstract: In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

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