公开(公告)号：US20230198422A1

公开(公告)日：2023-06-22

申请号：US18169113

申请日：2023-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Vivek Kishorechand Arora ,  Makoto Shibuya ,  Kengo Aoya

IPC: H02M7/527 ,  H02M3/00 ,  H01L29/16 ,  H02M7/00 ,  H01L29/20 ,  H02M3/158

CPC classification number: H02M7/527 ,  H02M3/003 ,  H01L29/1608 ,  H02M7/003 ,  H01L29/2003 ,  H02M3/1582

Abstract: A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.

公开(公告)号：US20230187306A1

公开(公告)日：2023-06-15

申请号：US17547698

申请日：2021-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rongwei Zhang ,  Woochan Kim ,  Patrick Francis Thompson

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L25/0655 ,  H01L24/48 ,  H01L21/4882 ,  H01L2224/48138 ,  H01L2224/48158

Abstract: An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.

公开(公告)号：US20230059142A1

公开(公告)日：2023-02-23

申请号：US17404765

申请日：2021-08-17

Applicant: Texas Instruments Incorporated

Inventor： Vivek Arora ,  Woochan Kim ,  Anindya Poddar

IPC: H01L23/433 ,  H01L23/31 ,  H01L23/00 ,  H01L23/495

Abstract: In a described example, an apparatus includes: a package substrate having a die mount surface; semiconductor die flip chip mounted to the package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the active surface of the semiconductor die and connected to the package substrate by solder joints; a thermal interposer comprising a thermally conductive material positioned over and in thermal contact with a backside surface of the semiconductor die; and mold compound covering a portion of the package substrate, a portion of the thermal interposer, the semiconductor die, and the post connects, the thermal interposer having a surface exposed from the mold compound.

公开(公告)号：US11410875B2

公开(公告)日：2022-08-09

申请号：US16225875

申请日：2018-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hau Thanh Nguyen ,  Woochan Kim ,  Yi Yan ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar ,  Masamitsu Matsuura ,  Kengo Aoya ,  Mutsumi Masumoto

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00

Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).

公开(公告)号：US11183441B2

公开(公告)日：2021-11-23

申请号：US16808018

申请日：2020-03-03

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

公开(公告)号：US20210202357A1

公开(公告)日：2021-07-01

申请号：US16840407

申请日：2020-04-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya Poddar ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16

Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.

公开(公告)号：US20200235067A1

公开(公告)日：2020-07-23

申请号：US16253680

申请日：2019-01-22

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Dibyajat Mishra ,  Kurt Sincerbox ,  Vivek Arora

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/07 ,  H01L25/00

Abstract: A packaged electronic device includes a multilayer substrate, including a first side, a first layer having a first plurality of conductive structures along the first side, and a second layer having a second plurality of conductive structures, a semiconductor die soldered to a first set of the conductive structures, a conductive clip directly connected to one of the conductive structures of the first layer and to a second side of the semiconductor die, and a package structure that encloses the semiconductor die and a portion of the conductive clip.

公开(公告)号：US20190385924A1

公开(公告)日：2019-12-19

申请号：US16008119

申请日：2018-06-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00

Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

公开(公告)号：US20250022782A1

公开(公告)日：2025-01-16

申请号：US18901148

申请日：2024-09-30

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/482

Abstract: A semiconductor package includes a leadframe including leads and a die attach pad (DAP) inside the leads, and at least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side attached to a bottom side portion of the DAP. The package includes a mold compound and a heat slug having a top side and a bottom side positioned within a cavity defined by sidewalls of the mold compound. The heat slug has an area greater than an area of the DAP is attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. Bondwires are between the leads and the bond pads. Exposed from the mold compound is a bottom side surfaces of the leads and the top side of the heat slug.

公开(公告)号：US12154861B2

公开(公告)日：2024-11-26

申请号：US16669666

申请日：2019-10-31

Applicant: Texas Instruments Incorporated

Inventor： Woochan Kim ,  Masamitsu Matasuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar ,  Hideaki Matsunaga

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.