公开(公告)号：US11594618B2

公开(公告)日：2023-02-28

申请号：US17113512

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Huicheng Chang ,  Liang-Yin Chen

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

Abstract: A finFET device and methods of forming a finFET device are provided. The device includes a fin and a capping layer over the fin. The device also includes a gate stack over the fin, the gate stack including a gate electrode and a gate dielectric. The gate dielectric extends along sidewalls of the capping layer. The device further includes a gate spacer adjacent to sidewalls of the gate electrode, the capping layer being interposed between the gate spacer and the fin.

公开(公告)号：US20220415719A1

公开(公告)日：2022-12-29

申请号：US17459164

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/66 ,  H01L21/265 ,  H01L23/544 ,  H01J37/317 ,  H01J37/20 ,  H01J37/304 ,  H01J37/22

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

公开(公告)号：US20220406592A1

公开(公告)日：2022-12-22

申请号：US17651851

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/3213

Abstract: A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.

公开(公告)号：US20220293448A1

公开(公告)日：2022-09-15

申请号：US17199980

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chih-Kai Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/68 ,  H01L23/544 ,  G06T7/73 ,  G06T1/00 ,  G06T7/00

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

公开(公告)号：US20210226008A1

公开(公告)日：2021-07-22

申请号：US17201041

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Maio Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20210091209A1

公开(公告)日：2021-03-25

申请号：US17113512

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Huicheng Chang ,  Liang-Yin Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78

Abstract: A finFET device and methods of forming a finFET device are provided. The device includes a fin and a capping layer over the fin. The device also includes a gate stack over the fin, the gate stack including a gate electrode and a gate dielectric. The gate dielectric extends along sidewalls of the capping layer. The device further includes a gate spacer adjacent to sidewalls of the gate electrode, the capping layer being interposed between the gate spacer and the fin.

公开(公告)号：US10950694B2

公开(公告)日：2021-03-16

申请号：US16433374

申请日：2019-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Maio Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20200295135A1

公开(公告)日：2020-09-17

申请号：US16889356

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Liang-Yin Chen

IPC: H01L29/08 ,  H01L29/36 ,  H01L29/417 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/223 ,  H01L21/324 ,  H01L29/45 ,  H01L29/66

Abstract: Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region.

公开(公告)号：US10658508B2

公开(公告)日：2020-05-19

申请号：US16038866

申请日：2018-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/306 ,  H01L21/223 ,  H01L29/165

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes forming a modified region in the epitaxial structure. The modified region has lower crystallinity than an inner portion of the epitaxial structure and extends along an entirety of an exposed surface of the epitaxial structure. The method also includes forming a semiconductor-metal compound region on the epitaxial structure. All or some of the modified region is transformed into the semiconductor-metal compound region.

公开(公告)号：US20240203749A1

公开(公告)日：2024-06-20

申请号：US18415411

申请日：2024-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chia-Cheng Chen ,  Wei-Ting Chien ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/32 ,  G03F7/00 ,  H01L21/027

CPC classification number: H01L21/32 ,  G03F7/70283 ,  H01L21/027

Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.