公开(公告)号：US20230259036A1

公开(公告)日：2023-08-17

申请号：US18305536

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Huei Huang ,  Ya-Wen Chiu ,  Lun-Kuang Tan

IPC: G03F7/00 ,  H01J37/317 ,  H01L21/266 ,  H01L21/265 ,  H01J37/305

CPC classification number: G03F7/70033 ,  H01J37/317 ,  H01L21/266 ,  H01L21/26586 ,  H01J37/3056

Abstract: A method includes forming a resist pattern over a structure, the resist pattern having a trench surrounded by first resist walls extending lengthwise along a first direction and second resist walls extending lengthwise along a second direction perpendicular to the first direction. The method includes loading the structure and the resist pattern into an ion implanter so that a top surface of the resist pattern faces an ion travel direction of the ion implanter. The method includes tilting the structure and the resist pattern so that the ion travel direction forms a tilt angle with respect to an axis perpendicular to the top surface of the resist pattern. The method includes first rotating the structure and the resist pattern around the axis to a first position. The method includes first implanting ions into the resist pattern with the structure and the resist pattern at the first position.

公开(公告)号：US11222805B2

公开(公告)日：2022-01-11

申请号：US16837938

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chi Lin ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Jen Lo ,  Chih-Teng Liao

IPC: H01L21/683 ,  H01L21/3065 ,  H01J37/32

Abstract: A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus.

公开(公告)号：US10062787B2

公开(公告)日：2018-08-28

申请号：US15415790

申请日：2017-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ting Hsiao ,  Cheng-Ta Wu ,  Lun-Kuang Tan ,  Liang-Yu Yen ,  Ting-Chun Wang ,  Tsung-Han Wu ,  Wei-Ming You

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L23/535 ,  H01L29/66 ,  H01L21/3215

CPC classification number: H01L29/7856 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.

公开(公告)号：US11855092B2

公开(公告)日：2023-12-26

申请号：US17232309

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi Chen Ho ,  Yiting Chang ,  Lun-Kuang Tan ,  Chien Lin

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/6681 ,  H01L29/7851

Abstract: In an embodiment, a method includes forming a plurality of semiconductor fins over a substrate, the plurality of semiconductor fins comprising a first fin, a second fin, a third fin, and a fourth fin; forming a first dielectric layer over the plurality of semiconductor fins, the first dielectric layer filling an entirety of a first trench between the first fin and the second fin; forming a second dielectric layer over the first dielectric layer, the second dielectric layer filling an entirety of a second trench between the second fin and the third fin, the forming the second dielectric layer comprising: forming an oxynitride layer; and forming an oxide layer; and forming a third dielectric layer over the second dielectric layer, the third dielectric layer filling an entirety of a third trench between the third fin and the fourth fin.

公开(公告)号：US11532485B2

公开(公告)日：2022-12-20

申请号：US17107558

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Tsan-Chun Wang ,  Liang-Yin Chen ,  Jing-Huei Huang ,  Lun-Kuang Tan ,  Huicheng Chang

IPC: H01L21/31 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.

公开(公告)号：US20220359204A1

公开(公告)日：2022-11-10

申请号：US17870245

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Han Huang ,  Lun-Kuang Tan

IPC: H01L21/266 ,  H01L21/68 ,  H01J37/20 ,  H01J37/317

Abstract: Systems and methods are described herein for the variable and dynamic control of a variable aperture masking unit to define, isolate and/or mask diffusion areas for dopant implantation and/or thermal annealing processes useful in wafer fabrication in the production of advanced semiconductor devices. A plurality of isolation material panels can be dynamically positioned to define a size, position and shape of a variable mask aperture between edges of the plurality of isolation material panels. The isolation material panels are connected between cooperating pairs of carriers that are coupled to and travel along a set of parallel tracks on opposite sides of the variable aperture masking unit.

公开(公告)号：US11450741B2

公开(公告)日：2022-09-20

申请号：US17201041

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20190131399A1

公开(公告)日：2019-05-02

申请号：US15797703

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao LIU ,  Huicheng CHANG ,  Chia-Cheng CHEN ,  Liang-Yin CHEN ,  Kuo-Ju CHEN ,  Chun-Hung WU ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/265 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US12197131B2

公开(公告)日：2025-01-14

申请号：US18305536

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Huei Huang ,  Ya-Wen Chiu ,  Lun-Kuang Tan

IPC: G03F7/00 ,  H01J37/305 ,  H01J37/317 ,  H01L21/265 ,  H01L21/266

Abstract: A method includes forming a resist pattern over a structure, the resist pattern having a trench surrounded by first resist walls extending lengthwise along a first direction and second resist walls extending lengthwise along a second direction perpendicular to the first direction. The method includes loading the structure and the resist pattern into an ion implanter so that a top surface of the resist pattern faces an ion travel direction of the ion implanter. The method includes tilting the structure and the resist pattern so that the ion travel direction forms a tilt angle with respect to an axis perpendicular to the top surface of the resist pattern. The method includes first rotating the structure and the resist pattern around the axis to a first position. The method includes first implanting ions into the resist pattern with the structure and the resist pattern at the first position.

公开(公告)号：US12166127B1

公开(公告)日：2024-12-10

申请号：US18230419

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi Chen Ho ,  Yiting Chang ,  Lun-Kuang Tan ,  Chien Lin

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: In an embodiment, a method includes forming a plurality of semiconductor fins over a substrate, the plurality of semiconductor fins comprising a first fin, a second fin, a third fin, and a fourth fin; forming a first dielectric layer over the plurality of semiconductor fins, the first dielectric layer filling an entirety of a first trench between the first fin and the second fin; forming a second dielectric layer over the first dielectric layer, the second dielectric layer filling an entirety of a second trench between the second fin and the third fin, the forming the second dielectric layer comprising: forming an oxynitride layer; and forming an oxide layer; and forming a third dielectric layer over the second dielectric layer, the third dielectric layer filling an entirety of a third trench between the third fin and the fourth fin.