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    Seamless Bonding Layers In Semiconductor Packages and Methods of Forming the Same
    35.
    发明申请
    Seamless Bonding Layers In Semiconductor Packages and Methods of Forming the Same 有权

    公开(公告)号：US20230139919A1

    公开(公告)日：2023-05-04

    申请号：US17580942

    申请日：2022-01-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chia Hu ,  Ming-Fa Chen

    IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

    Abstract: Seamless bonding layers in semiconductor packages and methods of forming the same are disclosed. In an embodiment, a method includes forming a second passivation layer over a first metal pad and a second metal pad, the first metal pad and the second metal pad being disposed over a first passivation layer of a first semiconductor die; depositing a first bonding material over the second passivation layer to form a first portion of a first bonding layer, wherein at least a portion of a seam in the first bonding layer is between the first metal pad and the second metal pad; thinning the first portion of the first bonding layer to create a first opening from the seam; and re-depositing the first bonding material to fill the first opening and to form a second portion of the first bonding layer.

    Semiconductor device and method of manufacture
    37.
    发明授权
    Semiconductor device and method of manufacture 有权

    公开(公告)号：US11462458B2

    公开(公告)日：2022-10-04

    申请号：US17181784

    申请日：2021-02-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chia Hu ,  Sen-Bor Jan ,  Hsien-Wei Chen ,  Ming-Fa Chen

    IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L21/66 ,  H01L23/00

    Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

    Through-Dielectric Vias for Direct Connection and Method Forming Same
    38.
    发明申请
    Through-Dielectric Vias for Direct Connection and Method Forming Same 有权

    公开(公告)号：US20220262766A1

    公开(公告)日：2022-08-18

    申请号：US17229283

    申请日：2021-04-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Fa Chen ,  Chuan-An Cheng ,  Sung-Feng Yeh ,  Chih-Chia Hu

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L21/683 ,  H01L21/768 ,  H01L21/56 ,  H01L25/00

    Abstract: A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    40.
    发明申请
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210057309A1

    公开(公告)日：2021-02-25

    申请号：US16547606

    申请日：2019-08-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chia Hu ,  Hsien-Wei Chen ,  Ming-Fa Chen ,  Sen-Bor Jan

    IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00

    Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a semiconductor substrate, a plurality of interconnecting layers, a first connector, and a second connector. The semiconductor substrate includes a plurality of semiconductor devices therein. The interconnecting layers are disposed over the semiconductor substrate and electrically coupled to the semiconductor devices. The first connector is disposed over the plurality of interconnecting layers and extends to be in contact with a first level of the plurality of interconnecting layers. The second connector is disposed over the plurality of interconnecting layers and substantially leveled with the first connector. The second connector extends further than the first connector to be in contact with a second level of the plurality of interconnecting layers between the first level of the plurality of interconnecting layers and the semiconductor substrate, and the first connector is wider than the second connector.

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