公开(公告)号：US10714181B2

公开(公告)日：2020-07-14

申请号：US15799253

申请日：2017-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

IPC: G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

公开(公告)号：US10651114B2

公开(公告)日：2020-05-12

申请号：US16224159

申请日：2018-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Lin ,  Kao-Cheng Lin ,  Li-Wen Wang ,  Yen-Huei Chen

IPC: H01L23/48 ,  H01L25/065 ,  H01L27/06 ,  G11C5/06 ,  G11C7/18 ,  H01L27/10

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

公开(公告)号：US10411019B2

公开(公告)日：2019-09-10

申请号：US15186446

申请日：2016-06-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hidehiro Fujiwara ,  Wei-Min Chan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: H01L27/11 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528

Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.

公开(公告)号：US20190035455A1

公开(公告)日：2019-01-31

申请号：US15800443

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro FUJIWARA ,  Chih-Yu Lin ,  Sahil Preet Singh ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C11/419 ,  G11C7/12 ,  G11C8/08 ,  G11C5/14 ,  G11C11/4074 ,  H03K19/013

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

公开(公告)号：US09997235B2

公开(公告)日：2018-06-12

申请号：US15336633

申请日：2016-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng Wu ,  Chih-Yu Lin ,  Kao-Cheng Lin ,  Wei-Min Chan ,  Yen-Huei Chen

IPC: G11C5/14 ,  G11C7/00 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: A device is disclosed that includes first memory cells, second memory cells, a first conductive line and a second conductive line. The first conductive line is electrically disconnected from the second conductive line. The first conductive line receives a first power voltage for the plurality of first memory cells. The second conductive line receives a second power voltage that is independent from the first power voltage, for the plurality of second memory cells.