公开(公告)号：US20210398986A1

公开(公告)日：2021-12-23

申请号：US17035148

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Hsin NIEN ,  Chih-Yu LIN ,  Wei-Chang ZHAO ,  Hidehiro FUJIWARA

IPC: H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/8238

Abstract: A memory device is disclosed. The memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer, and a second portion of the second program line is formed in a third conductive layer above the second conductive layer. A width of at least one of the second portion of the first program line or the second portion of the second program line is different from a width of at least one of the first portion of the first program line or the first portion of the second program line. A method is also disclosed herein.

公开(公告)号：US20180151494A1

公开(公告)日：2018-05-31

申请号：US15453963

申请日：2017-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Yusuke ONIKI ,  Hidehiro FUJIWARA

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L23/5228 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5286 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/66545

Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.

公开(公告)号：US20250159857A1

公开(公告)日：2025-05-15

申请号：US19024672

申请日：2025-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hidehiro FUJIWARA ,  Wei-Min CHAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC: H10B10/00 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528 ,  H10D89/10

Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

公开(公告)号：US20250157531A1

公开(公告)日：2025-05-15

申请号：US19022593

申请日：2025-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Hsin NIEN ,  Wei-Chang ZHAO ,  Chih-Yu LIN ,  Hidehiro FUJIWARA ,  Yen-Huei CHEN ,  Ru-Yu WANG

IPC: G11C11/419 ,  G11C5/06 ,  G11C11/412

Abstract: A memory device includes a first word line and a second word line. The first word line is configured to transmit a first word line signal to a first set of memory cells. A first portion of the first word line is formed in a first metal layer, and a second portion of the first word line is formed in a second metal layer above the first metal layer. The second word line is configured to transmit a second word line signal to a second set of memory cells. A first portion of the second word line is formed in the first metal layer. A second portion of the second word line is formed in the second metal layer. The second portion of the first word line is partially overlapped with the second portion of the second word line.

公开(公告)号：US20230371227A1

公开(公告)日：2023-11-16

申请号：US18361384

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Hsin NIEN ,  Chih-Yu LIN ,  Wei-Chang ZHAO ,  Hidehiro FUJIWARA

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/8238

CPC classification number: H10B10/12 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283

Abstract: A memory device includes a first bit cell, a second bit cell, a first word line and a second word line. A first boundary of the second bit cell is adjacent with a first boundary of the first bit cell. The first word line is coupled to the first bit cell. The second word line is coupled to the second bit cell. A first segment of the first word line is overlapped with the first boundary of the second bit cell in a plan view, and a first segment of the second word line is overlapped with a second boundary of the second bit cell in the plan view.

公开(公告)号：US20190333584A1

公开(公告)日：2019-10-31

申请号：US16510168

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro FUJIWARA ,  Ching-Wei WU

IPC: G11C16/08 ,  G11C5/06 ,  G11C29/02 ,  G11C29/14 ,  G11C16/10 ,  G11C5/02 ,  G11C29/00 ,  G11C16/34 ,  G11C8/10

Abstract: A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.

公开(公告)号：US20240203488A1

公开(公告)日：2024-06-20

申请号：US18590490

申请日：2024-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Sahil Preet Singh ,  Hsien-Yu PAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418 ,  H03K19/013

CPC classification number: G11C11/419 ,  G11C5/147 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418 ,  H03K19/0136

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

公开(公告)号：US20200005858A1

公开(公告)日：2020-01-02

申请号：US16376640

申请日：2019-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Hsien-Yu PAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Sahil Preet SINGH

IPC: G11C11/419 ,  G11C11/412

Abstract: A read assist circuit is disclosed that selectively provides read assistance to a number of memory cells during a read operation of the number of memory cells. The read assist circuit includes a voltage divider circuit and a number of write line driver circuits. The voltage divider circuit is configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit to the number of write line driver circuits. Each write line driver circuit is configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line according to a corresponding individual enable signal that controls each write driver circuit. Further, each write line driver circuit is coupled to a corresponding memory cell of the number of memory cells via the corresponding write line so that the corresponding write line provides a corresponding write line voltage to provide read assistance during the read operation.

公开(公告)号：US20190080765A1

公开(公告)日：2019-03-14

申请号：US16160406

申请日：2018-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro FUJIWARA ,  Ching-Wei WU

IPC: G11C16/08 ,  G11C29/02 ,  G11C5/06 ,  G11C16/10 ,  G11C16/34 ,  G11C29/14 ,  G11C8/10 ,  G11C5/02 ,  G11C29/00 ,  G11C8/20 ,  G11C8/08

CPC classification number: G11C16/08 ,  G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C8/10 ,  G11C8/20 ,  G11C16/105 ,  G11C16/3481 ,  G11C29/024 ,  G11C29/025 ,  G11C29/14 ,  G11C29/783

Abstract: A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.

公开(公告)号：US20170110461A1

公开(公告)日：2017-04-20

申请号：US15186446

申请日：2016-06-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hidehiro FUJIWARA ,  Wei-Min CHAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC: H01L27/11 ,  H01L21/768 ,  H01L21/321 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L21/321 ,  H01L21/76838 ,  H01L23/5283

Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.