公开(公告)号：US20210183760A1

公开(公告)日：2021-06-17

申请号：US17188787

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Wen Shih ,  Chen-Hua Yu ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Sen-Kuei Hsu

IPC: H01L23/525 ,  H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56

Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

公开(公告)号：US20200335477A1

公开(公告)日：2020-10-22

申请号：US16923115

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US10756052B2

公开(公告)日：2020-08-25

申请号：US16524146

申请日：2019-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683 ,  H01L23/544

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US10748861B2

公开(公告)日：2020-08-18

申请号：US15980764

申请日：2018-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Han-Ping Pu ,  Yen-Ping Wang

IPC: H01L25/11 ,  H01L25/10 ,  H01L23/66 ,  H01L23/498 ,  H01L23/544 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation.

公开(公告)号：US20200091031A1

公开(公告)日：2020-03-19

申请号：US16693386

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Chao-Wen Shih ,  Han-Ping Pu ,  Hsin-Yu Pan ,  Sen-Kuei Hsu

IPC: H01L23/367 ,  H01L23/66 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/683 ,  H01Q1/02 ,  H01Q21/08

Abstract: A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.

公开(公告)号：US20200075526A1

公开(公告)日：2020-03-05

申请号：US16676439

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Kai Liu ,  Han-Ping Pu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/538

Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.

公开(公告)号：US10553533B2

公开(公告)日：2020-02-04

申请号：US15965978

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Nan-Chin Chuang

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L23/00

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.

公开(公告)号：US10366966B1

公开(公告)日：2019-07-30

申请号：US15981929

申请日：2018-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US20190139890A1

公开(公告)日：2019-05-09

申请号：US15965978

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Nan-Chin Chuang

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L23/00

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.

公开(公告)号：US20190096841A1

公开(公告)日：2019-03-28

申请号：US15717974

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Kai Liu ,  Han-Ping Pu ,  Ting-Chu Ko ,  Yung-Ping Chiang ,  Chang-Wen Huang ,  Yu-Sheng Hsieh

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/538

Abstract: Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.