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公开(公告)号:US11587922B2
公开(公告)日:2023-02-21
申请号:US17026900
申请日:2020-09-21
发明人: Ming-Fa Chen , Hsien-Wei Chen
IPC分类号: H01L25/00 , H01L23/00 , H01L23/538 , H01L23/48 , H01L21/768 , H01L23/31 , H01L25/03 , H01L21/56 , H01L25/10 , H01L25/18 , H01L25/065
摘要: A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.
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公开(公告)号:US20220384388A1
公开(公告)日:2022-12-01
申请号:US17884240
申请日:2022-08-09
发明人: Hsien-Wei Chen , Ming-Fa Chen
IPC分类号: H01L25/065 , H01L23/00 , H01L23/48 , H01L21/56 , H01L23/544
摘要: A package includes a first semiconductor substrate; an integrated circuit die bonded to the first semiconductor substrate with a dielectric-to-dielectric bond; a molding compound over the first semiconductor substrate and around the integrated circuit die; and a redistribution structure over the first semiconductor substrate and the integrated circuit die, wherein the redistribution structure is electrically connected to the integrated circuit die. The integrated circuit die includes a second semiconductor substrate, and wherein the second semiconductor substrate comprises a first sidewall, a second sidewall, and a third sidewall opposite the first sidewall and the second sidewall, and the second sidewall is offset from the first sidewall.
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公开(公告)号:US11508695B2
公开(公告)日:2022-11-22
申请号:US17195903
申请日:2021-03-09
发明人: Cheng-Hsien Hsieh , Li-Han Hsu , Wei-Cheng Wu , Hsien-Wei Chen , Der-Chyang Yeh , Chi-Hsi Wu , Chen-Hua Yu
IPC分类号: H01L25/065 , H01L23/538 , H01L25/00 , H01L25/10 , H01L23/00 , H01L21/56 , H01L23/31 , H01L23/498
摘要: An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
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公开(公告)号:US20220361332A1
公开(公告)日:2022-11-10
申请号:US17815373
申请日:2022-07-27
发明人: Cheng-Hsien Hsieh , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Hsien-Wei Chen , Li-Han Hsu , Wei-Cheng Wu
摘要: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
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公开(公告)号:US20220359470A1
公开(公告)日:2022-11-10
申请号:US17815390
申请日:2022-07-27
发明人: Chen-Hua Yu , An-Jhih Su , Wei-Yu Chen , Ying-Ju Chen , Tsung-Shu Lin , Chin-Chuan Chang , Hsien-Wei Chen , Wei-Cheng Wu , Li-Hsien Huang , Chi-Hsi Wu , Der-Chyang Yeh
IPC分类号: H01L25/065 , H01L21/48 , H01L21/56 , H01L21/78 , H01L23/31 , H01L23/498 , H01L25/00
摘要: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
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公开(公告)号:US20220359405A1
公开(公告)日:2022-11-10
申请号:US17813896
申请日:2022-07-20
发明人: Ming-Fa Chen , Sung-Feng Yeh , Hsien-Wei Chen
IPC分类号: H01L23/538 , H01L23/00 , H01L25/10 , H01L21/48 , H01L21/56 , H01L21/683 , H01L21/78 , H01L25/00 , H01L23/31
摘要: A package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.
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公开(公告)号:US11482649B2
公开(公告)日:2022-10-25
申请号:US16941556
申请日:2020-07-29
发明人: Ming-Fa Chen , Hsien-Wei Chen , Jie Chen
IPC分类号: H01L33/52 , H01L33/62 , H01L25/16 , H01L31/0232 , H01L31/0203 , H01L31/18 , H01L33/58 , G02B6/42 , G02B6/12
摘要: A semiconductor package includes a photonic die, an encapsulated electronic die, a substrate, and a lens structure. The photonic die includes an optical coupler. The encapsulated electronic die is disposed over and bonded to the photonic die. The encapsulated electronic die includes an electronic die and an encapsulating material at least laterally encapsulating the electronic die. The substrate is disposed over and bonded to the encapsulated electronic die. The lens structure is disposed over the photonic die and is overlapped with the optical coupler from a top view. The optical coupler is configured to be optically coupled to an optical signal source through the lens structure.
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公开(公告)号:US20220336393A1
公开(公告)日:2022-10-20
申请号:US17361924
申请日:2021-06-29
发明人: Hsien-Wei Chen , Ming-Fa Chen , Ying-Ju Chen
IPC分类号: H01L23/00 , H01L25/065 , H01L25/18 , H01L21/56 , H01L25/00
摘要: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.
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公开(公告)号:US11443995B2
公开(公告)日:2022-09-13
申请号:US17120859
申请日:2020-12-14
发明人: Chen-Hua Yu , Sung-Feng Yeh , Ming-Fa Chen , Hsien-Wei Chen , Tzuan-Horng Liu
IPC分类号: H01L23/495 , H01L23/31 , H01L23/538 , H01L23/48 , H01L23/522
摘要: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
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公开(公告)号:US11430670B2
公开(公告)日:2022-08-30
申请号:US17101608
申请日:2020-11-23
发明人: Hsien-Wei Chen , Der-Chyang Yeh , Li-Hsien Huang
IPC分类号: H01L23/00 , H01L21/56 , H01L23/31 , H01L25/065 , H01L25/10
摘要: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.
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