公开(公告)号：US20200058617A1

公开(公告)日：2020-02-20

申请号：US15998455

申请日：2018-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L25/00

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.

公开(公告)号：US20200043783A1

公开(公告)日：2020-02-06

申请号：US16600826

申请日：2019-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Kuan-Chieh Huang

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/762 ,  H01L23/522 ,  H01L23/48 ,  H01L27/06 ,  H01L21/822

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

公开(公告)号：US20180025970A1

公开(公告)日：2018-01-25

申请号：US15218488

申请日：2016-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Kuan-Chieh Huang

IPC: H01L23/528 ,  H01L27/088 ,  H01L21/265 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L23/538 ,  H01L29/06

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

公开(公告)号：US09397130B1

公开(公告)日：2016-07-19

申请号：US14583406

申请日：2014-12-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Chang Huang ,  Hsing-Chih Lin ,  Chien-Nan Tu ,  Yu-Lung Yeh

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689

Abstract: A semiconductor device includes a substrate, a semiconductor layer, light-sensing devices, a transparent dielectric layer and a grid shielding layer. The semiconductor layer overlies the substrate, and has a first surface and a second surface opposite to the first surface. The semiconductor layer includes microstructures disposed on the second surface of the semiconductor layer. The light-sensing devices are disposed on the first surface of the semiconductor layer. The transparent dielectric layer is disposed on the second surface of the semiconductor layer, and covers the microstructures. The grid shielding layer extends from the first surface of the semiconductor layer toward the second surface of the semiconductor layer, and surrounds each of the light-sensing devices to separate the light-sensing devices from each other, in which a depth of the grid shielding layer is greater than two-thirds of a thickness of the semiconductor layer.

Abstract translation: 半导体器件包括衬底，半导体层，光感测器件，透明电介质层和栅极屏蔽层。 半导体层覆盖在基板上，并且具有与第一表面相对的第一表面和第二表面。 半导体层包括设置在半导体层的第二表面上的微结构。 光感测装置设置在半导体层的第一表面上。 透明电介质层设置在半导体层的第二表面上并覆盖微结构。 栅极屏蔽层从半导体层的第一表面朝向半导体层的第二表面延伸，并且围绕每个光感测器件以彼此分离光感测器件，其中栅极屏蔽的深度 层的厚度大于半导体层厚度的三分之二。

公开(公告)号：US09269733B2

公开(公告)日：2016-02-23

申请号：US14329337

申请日：2014-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Nan Tu ,  Yu-Lung Yeh ,  Hsing-Chih Lin ,  Chien-Chang Huang

IPC: H01L23/52 ,  H01L27/146

CPC classification number: H01L27/14625 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14689

Abstract: A semiconductor device includes a substrate, a semiconductor layer and a switching element. The semiconductor layer is disposed on the substrate. The semiconductor layer has a light-sensing portion and includes microstructures at a side face area corresponding to the light-sensing portion. The switching element is disposed on the semiconductor layer. In the semiconductor device, the switching element and the light-sensing portion are staggered.

Abstract translation: 半导体器件包括衬底，半导体层和开关元件。 半导体层设置在基板上。 半导体层具有光感测部分，并且在对应于光感测部分的侧面区域中包括微结构。 开关元件设置在半导体层上。 在半导体装置中，开关元件和感光部分交错。

公开(公告)号：US12278250B2

公开(公告)日：2025-04-15

申请号：US17321909

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin ,  Feng-Chi Hung ,  Shyh-Fann Ting

IPC: H01L27/146

Abstract: A semiconductor device includes a substrate having a front side and a back side opposite to each other. A plurality of photodetectors is disposed in the substrate within a pixel region. An isolation structure is disposed within the pixel region and between the photodetectors. The isolation structure includes a back side isolation structure extending from the back side of the substrate to a position in the substrate. A conductive plug structure is disposed in the substrate within a periphery region. A conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. A conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap.

公开(公告)号：US11322481B2

公开(公告)日：2022-05-03

申请号：US16902539

申请日：2020-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

公开(公告)号：US11289455B2

公开(公告)日：2022-03-29

申请号：US16898613

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen ,  Che-Wei Chen

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

公开(公告)号：US20220084908A1

公开(公告)日：2022-03-17

申请号：US17177660

申请日：2021-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Wei Chuang Wu ,  Shih Kuang Yang ,  Hsing-Chih Lin ,  Jen-Cheng Liu

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L21/308

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance

公开(公告)号：US11217478B2

公开(公告)日：2022-01-04

申请号：US16600826

申请日：2019-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Kuan-Chieh Huang

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/762 ,  H01L23/522 ,  H01L23/48 ,  H01L27/06 ,  H01L21/822 ,  H01L23/525

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.