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公开(公告)号：US10270486B2
公开(公告)日：2019-04-23
申请号：US15900594
申请日：2018-02-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Feng-Wei Kuo , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , Robert Bogdan Staszewski , Sandro Binsfeld Ferreira
Abstract: An ultra-low-power receiver includes a low-noise amplifier configured to receive an input analog signal and generate an amplified signal and a mixer electrically coupled to the low-noise amplifier. The mixer is configured to convert said amplified signal into an intermediate frequency signal. A progressively reduced intermediate frequency filter is configured to process the intermediate frequency signal from the mixer in discrete time.
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公开(公告)号：US20190007088A1
公开(公告)日：2019-01-03
申请号：US15900594
申请日：2018-02-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Feng-Wei KUO , Chewn-Pu JOU , Huan-Neng Chen , Lan-Chou Cho , Robert Bogdan STASZEWSKI , Sandro Binsfeld FERREIRA
Abstract: An ultra-low-power receiver includes a low-noise amplifier configured to receive an input analog signal and generate an amplified signal and a mixer electrically coupled to the low-noise amplifier. The mixer is configured to convert said amplified signal into an intermediate frequency signal. A progressively reduced intermediate frequency filter is configured to process the intermediate frequency signal from the mixer in discrete time.
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公开(公告)号：US20230387180A1
公开(公告)日：2023-11-30
申请号：US18232332
申请日：2023-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Feng Wei KUO , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , Robert Bogdan Staszewski
IPC: H03L7/099 , H03L7/085 , C02F11/18 , B01D1/00 , H01F27/28 , C02F1/04 , C02F11/12 , H01L23/522 , B01D1/12 , C02F103/32 , C02F103/28 , C02F101/30 , C02F103/16 , C02F103/34 , C02F103/14 , C02F103/36
CPC classification number: H01L28/10 , H03L7/085 , H03L7/099 , C02F11/18 , B01D1/0017 , H01F27/2885 , C02F1/048 , C02F11/12 , H01L23/5227 , B01D1/12 , H03L2207/50 , C02F2103/32 , C02F2103/28 , C02F2101/301 , C02F2103/16 , C02F2103/343 , C02F2101/306 , C02F2103/14 , C02F2103/365
Abstract: In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.
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34.发明授权公开(公告)号：US11637078B2
公开(公告)日：2023-04-25
申请号：US17182155
申请日：2021-02-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Feng Wei Kuo , Wen-Shiang Liao , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , William Wu Shen
IPC: H01L23/66 , H01L23/552 , H01L23/498 , H01L23/00 , H01L25/18 , H01L23/522 , H01L25/065
Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.
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公开(公告)号：US11531159B2
公开(公告)日：2022-12-20
申请号：US17212934
申请日：2021-03-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern , Lan-Chou Cho , Huan-Neng Chen , Min-Hsiang Hsu , Feng-Wei Kuo , Chih-Chang Lin , Weiwei Song , Chewn-Pu Jou
Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
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Patent Agency Ranking
公开(公告)号：US20220317379A1
公开(公告)日：2022-10-06
申请号：US17220724
申请日：2021-04-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Tsung Shih , Chewn-Pu Jou , Stefan Rusu , Felix Ying-Kit Tsui , Lan-Chou Cho
Abstract: Disclosed are apparatus and methods for optical coupling. In one example, a described apparatus includes: a planar layer; a grating region comprising an array of scattering elements arranged in the planar layer to form a two-dimensional grating; a first taper structure formed in the planar layer connecting a first side of the grating region to a first waveguide, wherein a shape of the first taper structure is a first triangle that is asymmetric about any line perpendicular to the first side of the grating region in the planar layer; and a second taper structure formed in the planar layer connecting a second side of the grating region to a second waveguide, wherein a shape of the second taper structure is a second triangle that is asymmetric about any line perpendicular to the second side of the grating region in the planar layer, wherein the first side and the second side are substantially perpendicular to each other.
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37.发明授权公开(公告)号：US11409139B2
公开(公告)日：2022-08-09
申请号：US16897581
申请日：2020-06-10
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Feng-Wei Kuo , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho
Abstract: A semiconductor device includes: a transistor layer including components of at least one transistor, a waveguide having a long axis extending in a first direction, and an alpha interconnection layer over the waveguide; a stack of metallization layers over the transistor layer, the stack including one or more beta interconnection layers interposed between corresponding pairs of neighboring ones of the metallization layers; and a heater in the alpha interconnection layer or in one of the one or more beta interconnection layers; and wherein, relative to a second direction substantially perpendicular to the first direction, the heater substantially overlaps at least a portion of the waveguide.
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公开(公告)号：US20210396930A1
公开(公告)日：2021-12-23
申请号：US17212934
申请日：2021-03-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern , Lan-Chou Cho , Huan-Neng Chen , Min Hsiang Hsu , Feng-Wei Kuo , Chih-Chang Lin , Weiwei Song , Chewn-Pu Jou
Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the second waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
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公开(公告)号：US11156894B2
公开(公告)日：2021-10-26
申请号：US16804522
申请日：2020-02-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Lan-Chou Cho , Chewn-Pu Jou , Min-Hsiang Hsu
Abstract: Apparatus, circuits and methods for reducing mismatch in an electro-optic modulator are described herein. In some embodiments, a described optical includes: a splitter configured for splitting an input optical signal into a first optical signal and a second optical signal; a phase shifter coupled to the splitter; and a combiner coupled to the phase shifter. The phase shifter includes: a first waveguide arm configured for controlling a first phase of the first optical signal to generate a first phase-controlled optical signal, and a second waveguide arm configured for controlling a second phase of the second optical signal to generate a second phase-controlled optical signal. Each of the first and second waveguide arms includes: a plurality of straight segments and a plurality of curved segments. The combiner is configured for combining the first and second phase-controlled optical signals to generate an output optical signal.
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公开(公告)号：US20210193564A1
公开(公告)日：2021-06-24
申请号：US16984297
申请日：2020-08-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Chan-Hong Chern , Feng-Wei Kuo , Lan-Chou Cho , Stefan Rusu
IPC: H01L23/52 , G02B6/43 , H01L31/0232 , H01L31/18
Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.
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