公开(公告)号：US20190131414A1

公开(公告)日：2019-05-02

申请号：US15800474

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L21/265

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US09865748B2

公开(公告)日：2018-01-09

申请号：US15488325

申请日：2017-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L29/68 ,  H01L29/87 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/87 ,  H01L29/0607 ,  H01L29/66121

Abstract: A semiconductor structure includes a semiconductor substrate having a first electrical portion, a second electrical portion, and a bridged conductive layer. The first electrical portion includes a first semiconductor well, a second semiconductor well in the first semiconductor well, and a third semiconductor well and a fourth semiconductor well in the second semiconductor well. The second electrical portion includes a fifth semiconductor well, a semiconductor layer in the fifth semiconductor well, and a sixth semiconductor well and a seventh semiconductor well in the fifth semiconductor well. The semiconductor layer has separated first and second portions. The bridged conductive layer connects the fourth semiconductor well and the sixth semiconductor well.

公开(公告)号：US20160064394A1

公开(公告)日：2016-03-03

申请号：US14472496

申请日：2014-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Liang Chu ,  Ruey-Hsin Liu ,  Chih-Wen Albert Yao ,  Ming-Ta Lei

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/265 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L29/788 ,  H01L29/49

CPC classification number: H01L27/11521 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7883

Abstract: Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET.

Abstract translation: 本公开的一些实施例涉及包括闪存单元和金属氧化物半导体场效应晶体管（MOSFET）的嵌入式闪存（e-flash）存储器件。 闪存单元包括设置在浮动栅极上的控制栅极。 MOSFET包括设置在栅极电介质上的逻辑门。 逻辑门的浮置栅极和第一栅极层同时形成有第一多晶硅层。 然后，通过高温工艺在浮栅上形成高温氧化物（HTO），而第一栅极层由于高温处理而保护栅极电介质免受劣化影响。 然后通过第二多晶硅层在第一栅极层上形成逻辑门的第二栅极层。 第一和第二栅极层共同形成MOSFET的逻辑门。