公开(公告)号：US11107899B2

公开(公告)日：2021-08-31

申请号：US16837401

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US11444169B2

公开(公告)日：2022-09-13

申请号：US16929640

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Liang Chu ,  Chien-Chih Chou ,  Chih-Chang Cheng ,  Yi-Huan Chen ,  Kong-Beng Thei ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Ta-Yuan Kung

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L21/762

Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.

公开(公告)号：US20200343195A1

公开(公告)日：2020-10-29

申请号：US16924627

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L23/552 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/762

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

公开(公告)号：US09627551B2

公开(公告)日：2017-04-18

申请号：US14026580

申请日：2013-09-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L29/66 ,  H01L29/87

CPC classification number: H01L29/87 ,  H01L29/0607 ,  H01L29/66121

Abstract: The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein.

公开(公告)号：US09472665B2

公开(公告)日：2016-10-18

申请号：US14024872

申请日：2013-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7835 ,  H01L21/28052 ,  H01L21/28105 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/66659 ,  H01L29/7833

Abstract: A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability.

Abstract translation: 提供了一种新颖的MOS晶体管，其包括源极区，漏极区，沟道区，隔离区，漂移区，栅极介电层，栅电极和场板。 栅电极具有第一部分和第二部分。 第一导电类型的第一部分位于沟道区上方，并且具有等于或大于与沟道区重叠的栅电极的距离的宽度。 第二部分是未掺杂的并且位于隔离区上方。 因此，MOS晶体管允许更高的工艺自由度节省生产成本，并提高可靠性。

公开(公告)号：US09190476B2

公开(公告)日：2015-11-17

申请号：US14705007

申请日：2015-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ker Hsiao Huo ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/404 ,  H01L29/0607 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816

Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

Abstract translation: 横向DMOS晶体管设置有源极区，漏极区和导电栅。 漏极区域通过在导电栅极下方侵入的场氧化物与导电栅极横向分离。 横向DMOS晶体管可以形成为跑道状结构，其中导电栅极包括直线部分和弯曲部分并被源极区域包围。 布置在导电栅极和捕获的漏极之间是一层或多层次的层间电介质材料。 一组或多组隔离的导体引线形成在电介质层中或介质层上，并且可以设置在多个器件级。 隔离导电引线增加了横向DMOS晶体管的击穿电压，特别是在电场拥挤可能会降低击穿电压的弯曲区域中。

公开(公告)号：US09035379B2

公开(公告)日：2015-05-19

申请号：US14333886

申请日：2014-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ker Hsiao Huo ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/404 ,  H01L29/0607 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816

Abstract: A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.

公开(公告)号：US20200227528A1

公开(公告)日：2020-07-16

申请号：US16837401

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US09466715B2

公开(公告)日：2016-10-11

申请号：US14015350

申请日：2013-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/02

CPC classification number: H01L29/7833 ,  H01L21/0226 ,  H01L21/823462 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816

Abstract: A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously.

Abstract translation: 提供了包括阱区，栅介质层，栅电极，源区和漏区的新型MOS晶体管。 第一导电类型的阱区延伸到半导体衬底中。 栅介质层位于阱区上方。 栅电极位于栅介电层上。 与第一导电类型相反的第二导电类型的源极区域和第二导电类型的漏极区域位于栅极电极的阱区域和相对侧。 栅极电介质层具有分别最靠近源极区域和漏极区域的第一部分和第二部分。 第二部分的厚度大于第一部分的厚度，以便提高击穿电压并同时维持电流。

公开(公告)号：US11088085B2

公开(公告)日：2021-08-10

申请号：US16924627

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L23/552 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/762

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.