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    Selective Polysilicon Doping for Gate Induced Drain Leakage Improvement
    2.
    发明申请
    Selective Polysilicon Doping for Gate Induced Drain Leakage Improvement 审中-公开
    选择性多晶硅掺杂用于栅极引起的漏极泄漏改进

    公开(公告)号：US20160043188A1

    公开(公告)日：2016-02-11

    申请号：US14453304

    申请日：2014-08-06

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chen-Liang Chu ,  Chih-Wen Yao ,  Ruey-Hsin Liu ,  Ming-Ta Lei

    IPC分类号： H01L29/417 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786

    CPC分类号： H01L27/124 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/6659 ,  H01L29/7833

    摘要： Some embodiments of the present disclosure relate to deceasing off-state leakage current within a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes source and drain regions. The source and drain regions are separated by a channel region. A gate is arranged over the channel region. The gate has a first gate region adjacent to the source region and a second gate region adjacent to the drain region. The first gate region is selectively doped adjacent the source region. The second gate region is undoped or lightly-doped. The undoped or lightly-doped second gate region reduces the electric field between the gate and the drain region, and hence reduces a gate induced drain leakage (GIDL) current between the gate and drain region. The undoped or lightly-doped region of the gate can reduce the GIDL current within the MOSFET by about three orders of magnitude. Other embodiments are also disclosed.

    摘要翻译： 本公开的一些实施例涉及在金属氧化物半导体场效应晶体管（MOSFET）内去除截止状态的漏电流。 MOSFET包括源极和漏极区域。 源极和漏极区域被沟道区域分开。 在通道区域上设置一个门。 栅极具有与源极区域相邻的第一栅极区域和与漏极区域相邻的第二栅极区域。 第一栅极区域被选择性地掺杂在源极区附近。 第二栅极区域是未掺杂的或轻掺杂的。 未掺杂或轻掺杂的第二栅极区域减小栅极和漏极区域之间的电场，因此减小栅极和漏极区域之间的栅极感应漏极漏极（GIDL）电流。 栅极的未掺杂或轻掺杂区域可以将MOSFET内的GIDL电流降低约三个数量级。 还公开了其他实施例。

    Selective polysilicon doping for gate induced drain leakage improvement
    3.
    发明授权
    Selective polysilicon doping for gate induced drain leakage improvement 有权

    公开(公告)号：US10680019B2

    公开(公告)日：2020-06-09

    申请号：US16382455

    申请日：2019-04-12

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chen-Liang Chu ,  Chih-Wen Albert Yao ,  Ruey-Hsin Liu ,  Ming-Ta Lei

    IPC分类号： H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

    摘要： Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.

    Selective polysilicon doping for gate induced drain leakage improvement
    5.
    发明授权
    Selective polysilicon doping for gate induced drain leakage improvement 有权

    公开(公告)号：US10276596B2

    公开(公告)日：2019-04-30

    申请号：US14453304

    申请日：2014-08-06

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chen-Liang Chu ,  Chih-Wen Albert Yao ,  Ruey-Hsin Liu ,  Ming-Ta Lei

    IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/28

    摘要： Some embodiments of the present disclosure relate to deceasing off-state leakage current within a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes source and drain regions. The source and drain regions are separated by a channel region. A gate is arranged over the channel region. The gate has a first gate region adjacent to the source region and a second gate region adjacent to the drain region. The first gate region is selectively doped adjacent the source region. The second gate region is undoped or lightly-doped. The undoped or lightly-doped second gate region reduces the electric field between the gate and the drain region, and hence reduces a gate induced drain leakage (GIDL) current between the gate and drain region. The undoped or lightly-doped region of the gate can reduce the GIDL current within the MOSFET by about three orders of magnitude. Other embodiments are also disclosed.

    Integrated circuit for high-voltage device protection
    6.
    发明授权
    Integrated circuit for high-voltage device protection 有权
    用于高压器件保护的集成电路

    公开(公告)号：US09343465B2

    公开(公告)日：2016-05-17

    申请号：US14472496

    申请日：2014-08-29

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chen-Liang Chu ,  Ruey-Hsin Liu ,  Chih-Wen Albert Yao ,  Ming-Ta Lei

    IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265

    CPC分类号： H01L27/11521 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7883

    摘要： Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET.

    摘要翻译： 本公开的一些实施例涉及包括闪存单元和金属氧化物半导体场效应晶体管（MOSFET）的嵌入式闪存（e-flash）存储器件。 闪存单元包括设置在浮动栅极上的控制栅极。 MOSFET包括设置在栅极电介质上的逻辑门。 逻辑门的浮置栅极和第一栅极层同时形成有第一多晶硅层。 然后，通过高温工艺在浮栅上形成高温氧化物（HTO），而第一栅极层由于高温处理而保护栅极电介质免受劣化影响。 然后通过第二多晶硅层在第一栅极层上形成逻辑门的第二栅极层。 第一和第二栅极层共同形成MOSFET的逻辑门。

    Integrated Circuit for High-Voltage Device Protection
    9.
    发明申请
    Integrated Circuit for High-Voltage Device Protection 有权
    高压器件保护集成电路

    公开(公告)号：US20160064394A1

    公开(公告)日：2016-03-03

    申请号：US14472496

    申请日：2014-08-29

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chen-Liang Chu ,  Ruey-Hsin Liu ,  Chih-Wen Albert Yao ,  Ming-Ta Lei

    IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/265 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L29/788 ,  H01L29/49

    CPC分类号： H01L27/11521 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7883

    摘要： Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET.

    摘要翻译： 本公开的一些实施例涉及包括闪存单元和金属氧化物半导体场效应晶体管（MOSFET）的嵌入式闪存（e-flash）存储器件。 闪存单元包括设置在浮动栅极上的控制栅极。 MOSFET包括设置在栅极电介质上的逻辑门。 逻辑门的浮置栅极和第一栅极层同时形成有第一多晶硅层。 然后，通过高温工艺在浮栅上形成高温氧化物（HTO），而第一栅极层由于高温处理而保护栅极电介质免受劣化影响。 然后通过第二多晶硅层在第一栅极层上形成逻辑门的第二栅极层。 第一和第二栅极层共同形成MOSFET的逻辑门。