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    Conformal Transfer Doping Method for Fin-Like Field Effect Transistor
    32.
    发明申请
    Conformal Transfer Doping Method for Fin-Like Field Effect Transistor 有权

    公开(公告)号：US20220376090A1

    公开(公告)日：2022-11-24

    申请号：US17815857

    申请日：2022-07-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

    IPC: H01L29/66 ,  H01L21/265 ,  H01L21/225 ,  H01L29/165

    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

    Memory Array Including Dummy Regions
    34.
    发明申请
    Memory Array Including Dummy Regions 有权

    公开(公告)号：US20220358984A1

    公开(公告)日：2022-11-10

    申请号：US17815032

    申请日：2022-07-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chao-I Wu ,  Sheng-Chen Wang ,  Yu-Ming Lin

    IPC: G11C11/22 ,  H01L27/11597 ,  H01L27/1159 ,  H01L27/11587

    Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

    3D semiconductor package including memory array
    35.
    发明授权
    3D semiconductor package including memory array 有权

    公开(公告)号：US11444069B2

    公开(公告)日：2022-09-13

    申请号：US17138270

    申请日：2020-12-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Yu-Ming Lin

    IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L27/1159 ,  H01L27/11597 ,  H01L23/48 ,  H01L29/24

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

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