公开(公告)号：US11038061B2

公开(公告)日：2021-06-15

申请号：US16683559

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure over a substrate, a first dielectric layer adjacent to the fin structure, and a second dielectric layer covering a sidewall of the first dielectric layer. The first dielectric layer has a different etching selectivity than the second dielectric layer. A bottom portion of the second dielectric layer is lower than a bottom surface of the first dielectric layer. The semiconductor device structure also includes a source/drain feature over the fin structure and covering a sidewall of the second dielectric layer, nanostructures over the fin structure, and a gate stack wrapping around the nanostructures.

公开(公告)号：US11004960B2

公开(公告)日：2021-05-11

申请号：US16713199

申请日：2019-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first dielectric fin, a second dielectric fin, a semiconductor fin, an epitaxy structure, and a metal gate structure. The first dielectric fin and the second dielectric fin disposed over the substrate. The semiconductor fin is disposed over the substrate, in which the semiconductor fin is between the first dielectric fin and the second dielectric fin. The epitaxy structure covers at least two surfaces of the semiconductor fin, in which the epitaxy structure is in contact with the first dielectric fin and is separated from the second dielectric fin. The metal gate structure crosses the first dielectric fin, the second dielectric fin, and the semiconductor fin.

公开(公告)号：US11004959B2

公开(公告)日：2021-05-11

申请号：US16683512

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Zhi-Chang Lin ,  Kuan-Ting Pan ,  Chih-Hao Wang ,  Shi-Ning Ju

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L21/033 ,  H01L21/8234

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked wire structure and a second stacked wire structure extending above the isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first stacked wire structure and the second stacked wire structure. The semiconductor device structure also includes a capping layer formed over the dummy fin structure. The isolation structure has a first width, the dummy fin structure has a second width, and the second width is smaller than the first width.

公开(公告)号：US10854723B2

公开(公告)日：2020-12-01

申请号：US15665276

申请日：2017-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao Wang ,  Wai-Yi Lien ,  Shi-Ning Ju ,  Kai-Chieh Yang ,  Wen-Ting Lan

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/06

Abstract: According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.

公开(公告)号：US12278236B2

公开(公告)日：2025-04-15

申请号：US18444356

申请日：2024-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first and second semiconductive fins, a first dielectric layer, a first gate structure, a spacer layer, and an oxide material. The first dielectric layer is laterally between the first and second semiconductive fins. From a cross-sectional view taken along a direction perpendicular to a lengthwise direction of the first semiconductive fin, the first dielectric layer has a U-shaped profile. The first gate structure extends across the first and second semiconductive fins and the first dielectric layer. The spacer layer underlies the first dielectric layer and further extends to laterally surround a lower portion of the first dielectric layer, a lower portion of the first semiconductive fin, and a lower portion of the second semiconductive fin. The oxide material is nested in the first dielectric layer. A top surface of the oxide material is at an elevation higher than a top surface of the spacer layer.

公开(公告)号：US11676864B2

公开(公告)日：2023-06-13

申请号：US17005172

申请日：2020-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Shang-Wen Chang ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0886

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first fin, a second fin adjacent the first fin, and a third fin adjacent the second fin. The structure further includes a first source/drain epitaxial feature merged with a second source/drain epitaxial feature. The structure further includes a third source/drain epitaxial feature, and a first liner positioned at a first distance away from a first plane defined by a first sidewall of the first fin and a second distance away from a second plane defined by a second sidewall of the second fin. The first distance is substantially the same as the second distance, and the merged first and second source/drain epitaxial features is disposed over the first liner. The structure further includes a dielectric feature disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.

公开(公告)号：US11626509B2

公开(公告)日：2023-04-11

申请号：US17314763

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first dielectric fin, a semiconductor fin, a metal gate structure, an epitaxy structure, and a contact etch stop layer. The first dielectric fin is disposed over the substrate. The semiconductor fin is disposed over the substrate, in which along a lengthwise direction of the first dielectric fin and the semiconductor fin, the first dielectric fin is in contact with a first sidewall of the semiconductor fin. The metal gate structure crosses the first dielectric fin and the semiconductor fin. The epitaxy structure is over and in contact with the semiconductor fin. The contact etch stop layer is over and in contact with first dielectric fin.

公开(公告)号：US11569234B2

公开(公告)日：2023-01-31

申请号：US17027322

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuan-Ting Pan ,  Kuo-Cheng Chiang ,  Shi-Ning Ju ,  Yi-Ruei Jhan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/74 ,  H01L21/8234 ,  H01L21/768

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.

公开(公告)号：US11563106B2

公开(公告)日：2023-01-24

申请号：US16858891

申请日：2020-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/51

Abstract: Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.

公开(公告)号：US11502034B2

公开(公告)日：2022-11-15

申请号：US17027344

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lo-Heng Chang ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Shih-Cheng Chen ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238

Abstract: Corner portions of a semiconductor fin are kept on the device while removing a semiconductor fin prior to forming a backside contact. The corner portions of the semiconductor fin protect source/drain regions from etchant during backside processing. The corner portions allow the source/drain features to be formed with a convex profile on the backside. The convex profile increases volume of the source/drain features, thus, improving device performance. The convex profile also increases processing window of backside contact recess formation.