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    Semiconductor Packages and Methods of Forming
    31.
    发明公开
    Semiconductor Packages and Methods of Forming 审中-公开

    公开(公告)号：US20230395431A1

    公开(公告)日：2023-12-07

    申请号：US17830904

    申请日：2022-06-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Cheng-Chieh Li ,  Chih-Wei Wu ,  Ying-Ching Shih

    IPC: H01L21/822 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

    CPC classification number: H01L21/822 ,  H01L21/486 ,  H01L21/4857 ,  H01L24/16 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L21/565

    Abstract: A method of forming a semiconductor structure includes: forming a first redistribution structure on a first side of a wafer, the first redistribution structure including dielectric layers and conductive features in the dielectric layers; forming grooves in the first redistribution structure, the grooves exposing sidewalls of the dielectric layers and the wafer, the grooves defining a plurality of die attaching regions; bonding a plurality of dies to the first redistribution structure in the plurality of die attaching regions; forming a first molding material on the first side of the wafer around the plurality of dies, the first molding material filling the grooves; forming a passivation layer on a second side of the wafer opposing the first side; and dicing along the grooves from the second side of the wafer to form a plurality of individual semiconductor packages, each of the plurality of individual semiconductor packages including a respective die.

    Integrated Circuit Package and Method of Forming Same
    32.
    发明申请
    Integrated Circuit Package and Method of Forming Same 有权

    公开(公告)号：US20220359329A1

    公开(公告)日：2022-11-10

    申请号：US17872488

    申请日：2022-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu

    IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/18

    Abstract: An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.

    Semiconductor structure having a dielectric layer edge covering circuit carrier
    33.
    发明授权
    Semiconductor structure having a dielectric layer edge covering circuit carrier 有权

    公开(公告)号：US11410897B2

    公开(公告)日：2022-08-09

    申请号：US16454099

    申请日：2019-06-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

    IPC: H01L23/31 ,  H01L23/49 ,  H01L23/28 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498

    Abstract: A semiconductor structure includes a circuit carrier, a dielectric layer, a conductive terminal, a semiconductor die, and an insulating encapsulation. The circuit carrier includes a first surface and a second surface opposite to each other, a sidewall connected to the first and second surfaces, and an edge between the second surface and the sidewall. The dielectric layer is disposed on the second surface of the circuit carrier and extends to at least cover the edge of the circuit carrier. The conductive terminal is disposed on and partially embedded in the dielectric layer to be connected to the circuit carrier. The semiconductor die encapsulated by the insulating encapsulation is disposed on the first surface of the circuit carrier and electrically coupled to the conductive terminal through the circuit carrier.

    PACKAGE AND MANUFACTURING METHOD THEREOF
    37.
    发明申请
    PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210265306A1

    公开(公告)日：2021-08-26

    申请号：US16801171

    申请日：2020-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

    IPC: H01L25/065 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48

    Abstract: A package includes at least one memory component and an insulating encapsulation. The at least one memory component includes a stacked memory structure and a plurality of conductive posts. The stacked memory structure is laterally encapsulated in a molding compound. The conductive posts are disposed on an upper surface of the stacked memory structure. The upper surface of the stacked memory structure is exposed from the molding compound. The insulating encapsulation encapsulates the at least one memory component. The top surfaces of the conductive posts are exposed form the insulating encapsulation. A material of the molding compound is different a material of the insulating encapsulation.

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    39.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200350283A1

    公开(公告)日：2020-11-05

    申请号：US16934041

    申请日：2020-07-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ying-Ching Shih ,  Chih-Wei Wu ,  Szu-Wei Lu

    IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56

    Abstract: A manufacturing method of a semiconductor package includes the following steps. A chip is provided. The chip has an active surface and a rear surface opposite to the active surface. The chip includes conductive pads disposed at the active surface. A first solder-containing alloy layer is formed on the rear surface of the chip. A second solder-containing alloy layer is formed on a surface and at a location where the chip is to be attached. The chip is mounted to the surface and the first solder-containing alloy layer is aligned with the second solder-containing alloy layer. A reflow step is performed on the first and second solder-containing alloy layers to form a joint alloy layer between the chip and the surface.

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