公开(公告)号：US11715681B2

公开(公告)日：2023-08-01

申请号：US17460626

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Wei Chiu ,  Sao-Ling Chiu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/532 ,  H01L21/60

CPC classification number: H01L23/49822 ,  H01L21/486 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/19 ,  H01L23/49816 ,  H01L23/53228 ,  H01L23/53233 ,  H01L2021/6006 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2924/18162

Abstract: A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

公开(公告)号：US11552054B2

公开(公告)日：2023-01-10

申请号：US16916098

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Lin ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L23/04 ,  H01L23/31 ,  H01L23/36 ,  H01L23/16 ,  H01L21/56

Abstract: A package structure includes a semiconductor device, a circuit substrate and a heat dissipating lid. The semiconductor device includes a semiconductor die. The circuit substrate is bonded to and electrically coupled to the semiconductor device. The heat dissipating lid is bonded to the circuit substrate and thermally coupled to the semiconductor device, where the semiconductor device is located in a space confined by the heat dissipating lid and the circuit substrate. The heat dissipating lid includes a cover portion and a flange portion bonded to a periphery of the cover portion. The cover portion has a first surface and a second surface opposite to the first surface, where the cover portion includes a recess therein, the recess has an opening at the second surface, and a thickness of the recess is less than a thickness of the cover portion, where the recess is part of the space.

公开(公告)号：US20250149486A1

公开(公告)日：2025-05-08

申请号：US18433908

申请日：2024-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Jen Chang ,  Chung-Yu Lu ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Hsien-Pin Hu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes forming a first conductive pillar on an interposer; forming a second conductive pillar on the interposer, wherein the second conductive pillar includes a barrier layer; bonding a first semiconductor device to the first conductive pillar by a first bonding region that includes more inter-metallic compound than solder; and bonding the first semiconductor device to the second conductive pillar by a second bonding region that includes more solder than inter-metallic compound.

公开(公告)号：US11967546B2

公开(公告)日：2024-04-23

申请号：US17870099

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L23/5385 ,  H01L2224/023 ,  H01L2225/107

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US11728278B2

公开(公告)日：2023-08-15

申请号：US16561045

申请日：2019-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yu Lu ,  Ping-Kang Huang ,  Sao-Ling Chiu

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/49816 ,  H01L23/5385 ,  H01L25/105 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16235

Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.

公开(公告)号：US11373946B2

公开(公告)日：2022-06-28

申请号：US16830284

申请日：2020-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Huang ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Shang-Yun Hou

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

公开(公告)号：US20210407963A1

公开(公告)日：2021-12-30

申请号：US16916098

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Lin ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L23/04 ,  H01L23/31 ,  H01L23/36 ,  H01L23/16 ,  H01L21/56

Abstract: A package structure includes a semiconductor device, a circuit substrate and a heat dissipating lid. The semiconductor device includes a semiconductor die. The circuit substrate is bonded to and electrically coupled to the semiconductor device. The heat dissipating lid is bonded to the circuit substrate and thermally coupled to the semiconductor device, where the semiconductor device is located in a space confined by the heat dissipating lid and the circuit substrate. The heat dissipating lid includes a cover portion and a flange portion bonded to a periphery of the cover portion. The cover portion has a first surface and a second surface opposite to the first surface, where the cover portion includes a recess therein, the recess has an opening at the second surface, and a thickness of the recess is less than a thickness of the cover portion, where the recess is part of the space.

公开(公告)号：US20210366814A1

公开(公告)日：2021-11-25

申请号：US16881211

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US20210193550A1

公开(公告)日：2021-06-24

申请号：US16718211

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wensen Hung ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Chien-Yuan Huang ,  Chen-Hsiang Lao

IPC: H01L23/367 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.

公开(公告)号：US10978404B2

公开(公告)日：2021-04-13

申请号：US16548341

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yu Lu ,  Yao-Jen Chang ,  Sao-Ling Chiu

IPC: H01L23/544 ,  H01L21/027 ,  H01L21/308

Abstract: Method for fabricating a semiconductor structure is provided. First features are formed in a first product region of each die area in a material layer through a first mask. Second features are formed in a second product region of each die area in the material layer through a second mask. Third features are formed in a third product region of each die area in the material layer through a third mask. Fourth features are formed in a fourth product region of each die area in the material layer through a fourth mask. Fifth features are formed in an alignment region of each die area in the material layer through the first through fourth masks. The first product region is adjacent to and in physical contact with the second and third product regions, and the first product region is free of the second, third, and fourth features.