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公开(公告)号：US20240249784A1
公开(公告)日：2024-07-25
申请号：US18626971
申请日：2024-04-04
发明人： Perng-Fei Yuh , Tung-Cheng Chang , Gu-Huan Li , Chia-En Huang , Chun-Ying Lee , Yih Wang
摘要： A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
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公开(公告)号：US20230386536A1
公开(公告)日：2023-11-30
申请号：US18232542
申请日：2023-08-10
发明人： Perng-Fei Yuh , Yih Wang
CPC分类号： G11C7/1096 , G11C8/08 , G11C7/12 , G11C7/1069 , G11C11/407
摘要： Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.
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33.发明公开公开(公告)号：US20230298665A1
公开(公告)日：2023-09-21
申请号：US18300706
申请日：2023-04-14
发明人： Perng-Fei Yuh , Yih Wang , Ku-Feng Lin , Jui-Che Tsai , Hiroki Noguchi , Fu-An Wu
IPC分类号： G11C14/00 , G11C11/419 , G11C11/16
CPC分类号： G11C14/0081 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/419
摘要： Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
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公开(公告)号：US11735280B2
公开(公告)日：2023-08-22
申请号：US17401907
申请日：2021-08-13
发明人： Gu-Huan Li , Tung-Cheng Chang , Perng-Fei Yuh , Chia-En Huang , Chun-Ying Lee , Yih Wang
摘要： A memory device is disclosed, including a bit cell storing a bit data. The bit cell includes multiple first transistors coupled to a node, multiple second transistors each coupled in series to a corresponding one of the first transistors, and at least one third transistor. The first transistors are turned on in response to a control signal. The second transistors are turned on in response to a first word line signal. The at least one third transistor has a control terminal to receive a second word line signal. In a programming mode of the memory device, the at least one third transistor provides, in response to the second word line signal, an adjust voltage to the node. The adjust voltage is associated with a voltage level of a first terminal of the at least one third transistor.
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公开(公告)号：US20230238042A1
公开(公告)日：2023-07-27
申请号：US17584127
申请日：2022-01-25
发明人： Perng-Fei Yuh , Yih Wang
CPC分类号： G11C7/1096 , G11C8/08 , G11C7/12 , G11C7/1069 , G11C17/18
摘要： Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.
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36.发明授权公开(公告)号：US11657873B2
公开(公告)日：2023-05-23
申请号：US17409341
申请日：2021-08-23
发明人： Perng-Fei Yuh , Yih Wang , Ku-Feng Lin , Jui-Che Tsai , Hiroki Noguchi , Fu-An Wu
IPC分类号： G11C14/00 , G11C11/419 , G11C11/16
CPC分类号： G11C14/0081 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/419
摘要： Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
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公开(公告)号：US20230057357A1
公开(公告)日：2023-02-23
申请号：US17407451
申请日：2021-08-20
发明人： Ku-Feng Lin , Jui-Che Tsai , Perng-Fei Yuh , Yih Wang
摘要： A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.
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公开(公告)号：US20220366956A1
公开(公告)日：2022-11-17
申请号：US17816143
申请日：2022-07-29
发明人： Perng-Fei Yuh
IPC分类号： G11C11/22 , G11C11/56 , H01L27/11585
摘要： A memory device includes a plurality of memory cells. Each memory cell includes a multi-gate FeFET that has a first source/drain terminal, a second source/drain terminal, and a gate with a plurality of ferroelectric layers configured such that each of the ferroelectric layers has a respective unique switching E-field.
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公开(公告)号：US20210398580A1
公开(公告)日：2021-12-23
申请号：US17229194
申请日：2021-04-13
发明人： Perng-Fei Yuh
IPC分类号： G11C11/22 , H01L27/11585 , G11C11/56
摘要： A memory device includes a plurality of memory cells. Each memory cell includes a multi-gate FeFET that has a first source/drain terminal, a second source/drain terminal, and a gate with a plurality of ferroelectric layers configured such that each of the ferroelectric layers has a respective unique switching E-field.
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公开(公告)号：US12094558B2
公开(公告)日：2024-09-17
申请号：US18318264
申请日：2023-05-16
发明人： Perng-Fei Yuh , Meng-Sheng Chang , Tung-Cheng Chang , Yih Wang
CPC分类号： G11C5/147 , G11C7/1084 , G11C17/165 , G11C17/18
摘要： One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.
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