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    Image processor
    33.
    发明授权
    Image processor 失效
    图像处理器

    公开(公告)号：US4635292A

    公开(公告)日：1987-01-06

    申请号：US682321

    申请日：1984-12-17

    申请人： Toshiki Mori ,  Haruyasu Yamada ,  Kenichi Hasegawa ,  Kunitoshi Aono

    发明人： Toshiki Mori ,  Haruyasu Yamada ,  Kenichi Hasegawa ,  Kunitoshi Aono

    IPC分类号： G06T5/20 ,  G06F9/28 ,  G06F15/66 ,  G06K9/36

    CPC分类号： G06T5/20

    摘要： This invention provides parallel partial image processing such as spatial convolution or non-linear neighbor arithmetic operation using an image processor which can easily be formed as a large-scale integrated circuit and can be used for various purposes. The image processor has an adder-subtractor, a multiplier, a reciprocal number memory in which the reciprocal of an address and the amount of shift are stored at each address, and a shift register. The processor therefore is capable of high-speed dividing operations by multiplying a multiplicant by the reciprocal of a multiplier and by shifting the result of the multiplication. Also, by switching the inputs to the adder-subtractor and to the multiplier rapidly under program control, it is possible to perform arbitrary addition, subtraction, multiplication and division on partial image data of m rows and n columns stored in a partial image memory of the image processor.

    摘要翻译： 本发明提供并行部分图像处理，例如使用可以容易地形成为大规模集成电路并可用于各种目的的图像处理器的空间卷积或非线性相邻算术运算。 图像处理器具有加法器 - 减法器，乘法器，互易数存储器，其中地址的倒数和移位量存储在每个地址处，以及移位寄存器。 因此，处理器能够通过将乘数乘以乘法器的倒数并通过移位乘法结果来进行高速分频操作。 此外，通过在程序控制下将输入切换到加法器 - 减法器和乘法器，可以对存储在部分图像存储器中的m行和n列的部分图像数据执行任意加法，减法，乘法和除法 图像处理器。

    Semiconductor memory having function to determine semiconductor low current
    35.
    发明授权
    Semiconductor memory having function to determine semiconductor low current 有权
    具有确定半导体低电流功能的半导体存储器

    公开(公告)号：US07636263B2

    公开(公告)日：2009-12-22

    申请号：US11905646

    申请日：2007-10-03

    申请人： Toshiki Mori

    发明人： Toshiki Mori

    IPC分类号： G11C16/04

    CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C2029/5006

    摘要： A semiconductor memory, including word lines, bit lines, memory cells provided at intersections between the word lines and bit lines, and a sense amplifier for reading out what is stored in the memory cells, bit line selection means for selecting a bit line from among the bit lines; switch means for turning ON/OFF a current of the bit line selected by the bit line selection means; current generation means for generating a threshold current; means for extracting a differential current between the selected bit line current and the threshold current when a value of the selected bit line current is greater than that of the threshold current; voltage conversion means for converting the differential current to a voltage; and determination means for determining a magnitude relationship between the threshold current and the selected bit line current based on an output voltage from the voltage conversion means.

    摘要翻译： 一种半导体存储器，包括字线，位线，提供在字线和位线之间的交叉处的存储单元，以及用于读出存储在存储单元中的内容的读出放大器，位线选择装置，用于从 位线 用于接通/关闭由位线选择装置选择的位线的电流的开关装置; 用于产生阈值电流的电流产生装置; 用于当所选位线电流的值大于阈值电流的值时，提取所选位线电流与阈值电流之间的差分电流的装置; 电压转换装置，用于将差分电流转换成电压; 以及确定装置，用于基于来自电压转换装置的输出电压确定阈值电流与所选位线电流之间的大小关系。

    Telephone system, its log-in management method and server device
    36.
    发明授权
    Telephone system, its log-in management method and server device 失效
    电话系统，其登录管理方法和服务器设备

    公开(公告)号：US07599358B2

    公开(公告)日：2009-10-06

    申请号：US11441245

    申请日：2006-05-26

    申请人： Toshiki Mori ,  Yoshiro Osaki

    发明人： Toshiki Mori ,  Yoshiro Osaki

    IPC分类号： H04L12/66

    CPC分类号： H04L65/1073

    摘要： A telephone system, comprising telephone sets, exchange device and server device, wherein a telephone set has notification unit accepting log-in operation and server device includes user management table associating each telephone number of telephone sets with identification information of users, address management table dynamically associating each telephone number of users with address information, specification processor specifies telephone number of logged-in user when log-in operation is performed, verification processor verifies presence/absence of registration of specified telephone number, determination processor determines coincidence/discordance between address information and notified address information, and update processor updates address management table by overwriting address information, if the notified address information does not coincide with address information corresponding to registered telephone number.

    摘要翻译： 一种电话系统，包括电话机，交换设备和服务器设备，其中电话机具有接收登录操作的通知单元，服务器设备包括将电话机的每个电话号码与用户的识别信息相关联的用户管理表，动态地址管理表 将每个电话号码与地址信息相关联，指定处理器指定登录操作时登录用户的电话号码，验证处理器验证是否存在指定电话号码的注册，确定处理器确定地址信息之间的一致/不一致 并通知地址信息，并且如果通知的地址信息与对应于注册的电话号码的地址信息不一致，则通过重写地址信息来更新处理器更新地址管理表。

    Semiconductor memory device, and read method and read circuit for the same
    37.
    发明授权
    Semiconductor memory device, and read method and read circuit for the same 有权
    半导体存储器件，以及读取方法和读取电路相同

    公开(公告)号：US07480183B2

    公开(公告)日：2009-01-20

    申请号：US11783799

    申请日：2007-04-12

    申请人： Toshiki Mori

    发明人： Toshiki Mori

    IPC分类号： G11C11/34

    CPC分类号： G11C16/24 ,  G11C16/28

    摘要： In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation. The reset state of a bit line is canceled when selected and connected to a read circuit for read, and information stored in a selected memory cell is read via the selected bit line. Upon completion of the read of the memory cell, the selected bit line is disconnected from the read circuit and reset to thereby complete discharge of residual charge in the read bit line prior to read operation in the next cycle. This ensures that during read determination operation in the next read cycle, the potential of a selected bit line will not vary with the bit line residual discharge in the previous read cycle.

    摘要翻译： 在可读取周期中对读取位线中剩余电荷进行放电的半导体存储器件中，除了读取操作之外，位线始终处于复位状态。 当选择并且连接到读取电路进行读取时，位线的复位状态被取消，并且通过所选择的位线读取存储在所选存储单元中的信息。 在完成存储单元的读取之后，所选择的位线与读取电路断开连接并重置，从而在下一个周期的读取操作之前完成读取位线中的剩余电荷的放电。 这确保了在下一个读取周期的读取确定操作期间，所选位线的电位将不会随先前读取周期中的位线残留放电而变化。

    Non-volatile semiconductor memory device
    38.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US07417898B2

    公开(公告)日：2008-08-26

    申请号：US11436632

    申请日：2006-05-19

    申请人： Toshiki Mori

    发明人： Toshiki Mori

    IPC分类号： G11C11/34

    CPC分类号： G11C16/28 ,  G11C11/5671 ,  G11C2211/5634

    摘要： Charge is trapped into a charge trapping region of one of two reference cells so as to achieve a state equivalent to memory cell characteristics having a smallest amount of current. Charge is trapped into a charge trapping region of the other reference cell so as to achieve a state equivalent to memory cell characteristics having a largest amount of current. Currents output from these reference cells are averaged by a current averaging circuit, and the resultant average current is output as a reference current R_REF 1.

    摘要翻译： 电荷被捕获到两个参考单元之一的电荷捕获区域中，以达到等效于具有最小电流量的存储单元特性的状态。 电荷被捕获到另一参考单元的电荷捕获区域中，以达到与具有最大电流量的存储单元特性相当的状态。 通过电流平均电路对这些参考单元输出的电流进行平均，并将合成的平均电流作为参考电流R_REF1输出。

    Semiconductor memory having function to determine semiconductor low current
    39.
    发明申请
    Semiconductor memory having function to determine semiconductor low current 有权
    具有确定半导体低电流功能的半导体存储器

    公开(公告)号：US20080170445A1

    公开(公告)日：2008-07-17

    申请号：US11905646

    申请日：2007-10-03

    申请人： Toshiki Mori

    发明人： Toshiki Mori

    IPC分类号： G11C29/50

    CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C2029/5006

    摘要： A semiconductor memory, including a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at intersections between the plurality of word lines and the plurality of bit lines, and a sense amplifier for reading out what is stored in the memory cells, the semiconductor memory including: bit line selection means for selecting a bit line from among the plurality of bit lines; switch means for turning ON/OFF a current of the bit line selected by the bit line selection means; current generation means for generating a threshold current; means for extracting a differential current between the selected bit line current and the threshold current when a value of the selected bit line current is greater than that of the threshold current; voltage conversion means for converting the differential current to a voltage; and determination means for determining a magnitude relationship between the threshold current and the selected bit line current based on an output voltage from the voltage conversion means.

    摘要翻译： 一种半导体存储器，包括多个字线，多个位线，设置在多个字线和多个位线之间的交叉处的多个存储单元，以及读出放大器，用于读出存储在 存储单元，所述半导体存储器包括：位线选择装置，用于从所述多个位线中选择位线; 用于接通/关闭由位线选择装置选择的位线的电流的开关装置; 用于产生阈值电流的电流产生装置; 用于当所选位线电流的值大于阈值电流的值时，提取所选位线电流与阈值电流之间的差分电流的装置; 电压转换装置，用于将差分电流转换成电压; 以及确定装置，用于基于来自电压转换装置的输出电压确定阈值电流与所选位线电流之间的大小关系。